论文信息 - Lumped electro-thermal model of on-chip interconnects

Lumped electro-thermal model of on-chip interconnects

The paper proposes a compact but accurate electro-thermal model of a long on-chip interconnect embedded in a ULSI circuit. The model is well suited to be interfaced with the commercially available tools employed in ICs design for interconnect parasitic extraction.

Paolo Maffezzoni | Lorenzo Codecasa | Dario D'Amore | N. Spennagallo

[1] Paolo Maffezzoni,et al. Measurements and extractions of parasitic capacitances in ULSI layouts , 2003 .

[2] A. Bilotti. Static temperature distribution in IC chips with isothermal heat sources , 1974 .

[3] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4] Dae-Mann Kim,et al. On-chip characterization of interconnect parameters and time delay in 0.18 /spl mu/m CMOS technology for ULSI circuit applications , 2000 .

[5] F. Caignet,et al. The challenge of signal integrity in deep-submicrometer CMOS technology , 2001, Proc. IEEE.

[6] Kaustav Banerjee,et al. Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7] R. V. Andrews. SOLVING CONDUCTIVE HEAT TRANSFER PROBLEMS WITH ELECTRICAL-ANALOGUE SHAPE FACTORS , 1955 .

[8] Kaustav Banerjee,et al. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.