Clock Network Power Saving Using Multi-Bit Flip-Flops in Multiple Voltage Island Design

Power consumption is an important issue in modern high-frequency and low power design. Multi-bit flip-flops are used to reduce the clock system power. The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption. In this paper, we propose an effective multi-bit flip-flops merging approach to deal with the clock network power minimization problem and an placement method to avoid placing flip-flops in the congestion bins. Moreover, the proposed approach can be applied to both single and multiple supply voltage designs. Experimental results show that our approach can reduced the clock power up to 25%. In addition, for multiple supply voltage designs, the proposed approach can reduce the number of level shifters significantly.