Synthesis of testable finite state machines

Three alternative approaches to the design of testable finite state machines (FSMs) are presented. Testability, in this context, refers to the effort of test generation. The testability implementation approaches are classified as presynthesis, during-synthesis or post-synthesis. For incorporating testability during synthesis, the FSM synthesis procedure is modified to produce a reduced feedback or pipeline-like structure which is easily analyzed by a sequential circuit test generator. In the presynthesis testability approach, a test function is added before logic synthesis. The test function guarantees test generation by a specific method, and the test hardware undergoes the same type of optimization as the functional hardware. For the post-synthesis approach, a partial scan method to break up the cyclic structure of the sequential circuit is described.<<ETX>>