Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes

Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we present a construction method for termination sequence generation circuits suitable for field-programmable gate arrays and application-specific integrated circuits. This method uses linear algebra to determine the termination sequence for a small number of states of the encoder and converts these solutions into a sequential circuit. Results are presented for several realizations of termination circuits for a (128,3,6) LDPC-CC

[1]  Xiaodai Dong,et al.  Low-density parity-check convolutional codes for Ethernet networks , 2005, PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005..

[2]  Rüdiger L. Urbanke,et al.  Efficient encoding of low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[3]  Michael Lentmaier,et al.  Implementation aspects of LDPC convolutional codes , 2008, IEEE Transactions on Communications.

[4]  Stephen Bates,et al.  A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[5]  P. Urard,et al.  A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  Shu Lin,et al.  A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols , 2003, IEEE Communications Letters.

[7]  Frank R. Kschischang,et al.  Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[8]  Xiaodai Dong,et al.  Low-density parity-check convolutional codes applied to packet based communication systems , 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

[9]  Keshab K. Parhi,et al.  A 54 Mbps (3,6)-regular FPGA LDPC decoder , 2002, IEEE Workshop on Signal Processing Systems.

[10]  Ramkrishna Swamy,et al.  Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[11]  Kamil Sh. Zigangirov,et al.  Time-varying periodic convolutional codes with low-density parity-check matrix , 1999, IEEE Trans. Inf. Theory.

[12]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[13]  Daniel J. Costello,et al.  A new construction for low density parity check convolutional codes , 2002, Proceedings of the IEEE Information Theory Workshop.

[15]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[16]  Christian Schlegel,et al.  Trellis and turbo coding , 2004 .