In deeply nano-scaled technology nodes, the number of process variations of the circuits will be up to thousands. Although dimensionality reduction can reduce the complexity for circuit modeling, it always needs SPICE and Monte Carlo simulations. In this paper, a weight model of process variations for each individual cell is proposed, which is fed with the operation conditions. After that, a path process variation reduction method is proposed by considering the influence of the cell delay deviations and their weights. The proposed method is verified under ISCAS85 benchmark suite. When selecting the top 20% critical variations, the mean and standard deviation errors of the delay distribution in our method are merely 0.06% and 0.56% compared with the results from SPICE simulations. The model realizes a fast quantification of the process variation effects on any circuit without time-consuming training processes.