InGaAs Tunneling Field-Effect-Transistors With Atomic-Layer-Deposited Gate Oxides

In<sub>0.7</sub>Ga<sub>0.3</sub>As tunneling field-effect-transistors (TFETs) using the p<sup>+</sup> (6 nm)/undoped (6 nm) tunneling junction with 5-nm HfO<sub>2</sub> gate oxides have been demonstrated with an on-current of 50 μA/μm and a minimum subthreshold swing (SS) of 86 mV/dec. The impacts of tunneling junction structures on TFETs' performance have been investigated. It has been found that In<sub>0.7</sub>Ga<sub>0.3</sub>As TFETs with the p<sup>+</sup> (4 nm)/undoped (8 nm) tunneling junction provide ~ 80% higher on -currents than In<sub>0.7</sub>Ga<sub>0.3</sub>As TFETs with the p<sup>+</sup> (6 nm)/undoped (6 nm) junction, and In<sub>0.7</sub>Ga<sub>0.3</sub>As TFETs exhibit much higher on-currents than In<sub>0.53</sub>Ga<sub>0.47</sub>As TFETs. Different atomic-layer-deposited gate oxides have been used, and Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> bilayer gate oxides effectively improve the SS compared with HfO<sub>2</sub> single gate oxide. The effects of equivalent oxide thickness scaling and operating temperatures on the on-current, the SS, and the gate-bias-dependent Esaki diode behavior have been also investigated.

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