Combinational Design Using SystemVerilog

The chapter discusses about the important combinational design examples. Even this chapter is useful to understand the always@* versus always_comb procedural block and design description to infer the combinational logic. Most of the time, we need to use the multiplexers, decoders, encoders and priority encoders during the RTL design stage. The chapter covers the hardware description of these blocks, verification and synthesis strategies using the efficient SystemVerilog constructs.