Partition-based Routing Tree Algorithm with Obstacles

In this paper, we propose a hybrid algorithm to obtain the routing tree with obstacles. The algorithm divides the chip into a set of sub-regions and applies the proper method for each sub-region. First, two density functions are used to determine the density of the sub-regions and judge whether the chip or sub-region should be divided. Then, the proper algorithm is selected to construct the routing tree of each sub-region. So far, we develop two different routing algorithms with the different objective functions. The former that is based on the spanning-graph minimizes total wirelength with the long runtime. The latter is presented to speedup runtime while the total wirelength is very long. Finally, all sub-trees of the sub-regions are connected with the shortest paths. In other words, the hybrid method is presented to make tradeoff between total wirelength and runtime. Compared to (Feng et al., 2005), hybrid method improves total wirelength by 38.3% with accepted runtime.

[1]  Yang Yang,et al.  Rectilinear Steiner Minimal Tree among obstacles , 2003, ASICON 2003.

[2]  Andrew B. Kahng,et al.  A new class of iterative Steiner tree heuristics with good performance , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Yu Hu,et al.  An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane , 2006, ISPD '06.

[4]  Hai Zhou.  Efficient Steiner tree construction based on spanning graphs , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Majid Sarrafzadeh,et al.  Creating and exploiting flexibility in rectilinear Steiner trees , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Andrew B. Kahng,et al.  Highly scalable algorithms for rectilinear and octilinear Steiner trees , 2003, ASP-DAC '03.

[7]  Yiyu Shi,et al.  CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[8]  Chris C. N. Chu,et al.  Efficient rectilinear Steiner tree construction with rectilinear blockages , 2005, 2005 International Conference on Computer Design.

[9]  Chris C. N. Chu,et al.  Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design , 2005, ISPD '05.

[10]  Majid Sarrafzadeh,et al.  Creating and exploiting flexibility in Steiner trees , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Joseph L. Ganley,et al.  Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[12]  Feng Zhou,et al.  Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction , 2002, SLIP '02.

[13]  G. Yan,et al.  An-OARSMan: obstacle-avoiding routing tree construction with good length performance , 2005, ASP-DAC '05.

[14]  Mary Jane Irwin,et al.  An edge-based heuristic for Steiner routing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Jiri Soukup,et al.  Fast Maze Router , 1978, 15th Design Automation Conference.

[16]  Jason Cong,et al.  Routing tree construction under fixed buffer locations , 2000, Proceedings 37th Design Automation Conference.

[17]  Yao-Wen Chang,et al.  Efficient obstacle-avoiding rectilinear steiner tree construction , 2007, ISPD '07.

[18]  C. Y. Lee.  An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..