The effect of dielectric relaxation on charge-redistribution A/D converters

The authors examine the extent to which dielectric relaxation in typical monolithic capacitors degrades the performance of charge-redistribution analog-to-digital (A/D) converters. They present experimental device data from a monolithic capacitor test circuit, describe an empirical capacitor model fit to the measurements, and compare simulated A/D system errors with those observed in a monolithic, 10-b, 3.3-ms A/D converter. It is believed that these techniques for modeling and predicting A/D converter errors will play an important role in making appropriate technology decisions and in guiding system and circuit design of high-precision monolithic converters of the future