Variability Analysis of On-chip Graphene Interconnects at Subthreshold Regime

In today's modern era, zest for low power applications and miniaturized gadgets has increased tremendously. Operating devices and circuits in subthreshold region of operation is an optimum technique to attain low power requirements in the system. On-chip interconnects that connect and facilitate signal transmission between devices and different modules as well as provide power and clock connections are one of the dominating parts of system. At deep submicron technologies, interconnects majorly affect and are deciding output performance parameter. To get higher performance, copper on-chip interconnects have been replaced by next-generation graphene interconnects. At miniaturized technology nodes, variation due to temperature, fabrication process and environmental fluctuations crops up significantly that varies the system output in on-chip ICs. As a result, variability analysis of on-chip interconnects at nano regime in subthreshold region has become need of the hour. In the present paper, effective variability analysis of graphene interconnect in subthreshold region is presented for the first time to the best of the knowledge of authors. Process corner, parametric and Monte-Carlo analyses have been performed to determine variability effect in on-chip multilayer graphene nanoribbon (MLGNR) interconnects. The different variability analyses have been performed at 32nm technology node.