Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode
暂无分享,去创建一个
[1] D. Yakimets,et al. Limitations on Lateral Nanowire Scaling Beyond 7-nm Node , 2017, IEEE Electron Device Letters.
[2] Ali M. Niknejad,et al. BSIM—SPICE Models Enable FinFET and UTB IC Designs , 2013, IEEE Access.
[3] A. Mercha,et al. Lateral versus vertical gate-all-around FETs for beyond 7nm technologies , 2014, 72nd Device Research Conference.
[4] C. Sah,et al. Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors☆ , 1966 .
[5] A. Thean,et al. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs , 2016, IEEE Transactions on Electron Devices.
[6] Erdal Oruklu,et al. Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).
[7] J. A. Ott,et al. Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.
[8] K. J. Kuhn,et al. Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.
[9] Diederik Verkest,et al. Vertical GAAFETs for the Ultimate CMOS Scaling , 2015, IEEE Transactions on Electron Devices.
[10] Chenming Hu,et al. Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs , 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
[11] Diederik Verkest,et al. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node , 2015, IEEE Transactions on Electron Devices.