An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address

Large scale computing and applications with large data sets often cause high cache miss rate because of using array of structures or linked-list data structure. When traversing these data structures, the memory accesses may have constant long-strides across pages on virtual address (VA), but mostly scatter over the physical address (PA). Therefore, conventional stride prefetcher (SP) based on PA cannot prefetch data efficiently here. In this paper, we propose a hardware data prefetching design named Virtual Address-based Stride Prefetcher (VASP) to exploit the prefetch potential of long-stride access pattern on VA. VASP detects the access strides on VA including those cross pages, then it predicts a new VA and prefetches data after address translation. We implement VASP in the gem5 simulator and use SPEC CPU2006 integer benchmarks to evaluate its performance. Our simulation results show that, compared with SP, applying VASP to caches offers up to 43% performance improvement in the mcf benchmark, and improves the overall performance by 6%.