Silicon Verification of Improved Nagata Current Mirrors

This paper describes silicon verification of our improved peaking current mirror, originally invented by Nagata Minoru in 1966. Our improved MOS current mirror circuits are insensitive to wide range of power supply voltage variation and they are realized by addition of multiple current peaks. We show their chip design/measurement results, and their performance evaluation. The proposed circuits are simple (such as, no need for startup circuit), small yet well-insensitive to power supply voltage variations, and they can be widely used in analog ICs.

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