A Design Approach for Power-Optimized Fully Reconfigurable $\Delta \Sigma$ A/D Converter for 4G Radios

This paper presents a novel design approach for fully reconfigurable low-voltage delta-sigma analog-digital converters for next-generation wireless applications. This approach guides us to find the power-optimal solution corresponding to the specifications of various wireless standards by exploring single-loop feedback and feedforward topologies with different filter order, number of quantizer bits, and oversampling ratios. Unlike previous multimode designs, this approach provides a better power efficiency. Based on this approach, a system-level design of a digitally programmable delta-sigma modulator for 4G radios is presented.

[1]  Richard Schreier,et al.  An empirical study of high-order single-bit delta-sigma modulators , 1993 .

[2]  Zhaohui Huang,et al.  An architectural power estimator for analog-to-digital converters , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[3]  E. Riccio,et al.  A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[4]  Maurits Ortmanns,et al.  Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Andrea Baschirotto,et al.  Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[6]  J. Arias,et al.  A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers , 2006, IEEE Journal of Solid-State Circuits.

[7]  S. Mechnig,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .

[8]  Michael M. Miyamoto,et al.  An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  Robert H. M. van Veldhoven,et al.  A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  R.H.M. van Veldhoven.  A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003 .