Design, Automation, and Test in Europe

[1]  Neal Wingen,et al.  What If You Could Design Tomorrow's System Today? , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Giovanni Squillero,et al.  An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[3]  Binoy Ravindran,et al.  Lock-Free Synchronization for Dynamic Embedded Real-Time Systems , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[4]  Dietmar Heinz,et al.  An assembler driven verification methodology (ADVM) , 2005, Design, Automation and Test in Europe.

[5]  Takeshi Shimizu,et al.  A formal verification methodology for checking data integrity , 2005, Design, Automation and Test in Europe.

[6]  Wayne Luk,et al.  Evaluation of SystemC modelling of reconfigurable embedded systems , 2005, Design, Automation and Test in Europe.

[7]  Dimitrios Soudris,et al.  A partitioning methodology for accelerating applications in hybrid reconfigurable platforms , 2005, Design, Automation and Test in Europe.

[8]  Fernando Gehm Moraes,et al.  MultiNoC: a multiprocessing system enabled by a network on chip , 2005, Design, Automation and Test in Europe.

[9]  Abhijit Chatterjee,et al.  Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.

[10]  Gabriela Nicolescu,et al.  .NET framework - a solution for the next generation tools for system-level modeling and simulation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Pallab Dasgupta,et al.  Formal verification coverage: are the RTL-properties covering the design's architectural intent? , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[12]  Ian O'Connor,et al.  Design and behavioral modeling tools for optical network-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[13]  Román Hermida,et al.  Behavioural bitwise scheduling based on computational effort balancing , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[14]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  Andreas Gerstlauer,et al.  RTOS modeling for system level design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  P. T. Gonciari,et al.  Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[18]  Lorena Anghel,et al.  Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.

[19]  N. Jha,et al.  MOCSYN: multiobjective core-based single-chip system synthesis , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[20]  Rajendran Panda,et al.  CMOS combinational circuit sizing by stage-wise tapering , 1998, Proceedings Design, Automation and Test in Europe.