Assessment of 65nm subthreshold logic for smart RFID applications

Nowadays, new ultra-low-power electronic applications require small digital circuits with an increasing number of functionalities and an always decreasing power budget, but compensated by a weak constraint on performances. RFID is such an example of application. In this context, this paper explores the efficiency of 65nm subthreshold logic in an AES coprocessor for smart RFID. The power consumption of such a circuit synthesized with a commercial 65nm library at nominal 1.2V Vdd is 1.14μW at 100kHz. As the huge timing slack suggests, the supply voltage can be lowered to reduce the power. A recharacterized library down to 0.4V enables the synthesis of the circuit, still working at 100 kHz (worst-case process and temperature) with a power consumption of 57.5nW. Furthermore, the usefulness of the recharacterized library for logic synthesis in the subthreshold regime is demonstrated.