Assertion-Based Verification of Transaction Level Models

Transaction Level Modeling with SystemC has become a de-facto industry standard for modeling of system-on-chip designs. The correctness of these models is therefore of crucial importance. In this paper, we propose a novel methodology to apply AssertionBased Verification to Transaction Level Models. The novelty is based on two contributions: (1) Using Aspect-Oriented Programming techniques permits transaction recording without having to modify the existing TLM. (2) Mapping of transactions to Boolean signals and automatic event clock creation enables the concise formulation of assertions. In contrast to other approaches, our methodology allows direct Assertion-Based Verification of the TLM without the necessity of an additional abstract model.