Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption

Power consumption is a major design concern in current high-performance microprocessors. To deal with consumption, many systems apply Dynamic Voltage Scaling (DVS) techniques which dynamically change the system speed depending on the workload characteristics. DVS costs in a multicore system can be reduced by sharing the same DVS regulator among the cores. In this context, to handle energy efficiently, the workload must be properly balanced among the cores. This paper proposes a new heuristic algorithm to balance the workload in a coarse-grain multicore system. The algorithm works on hard real-time tasks and dynamically drives the frequency/voltage level in order to guarantee real-time constraints. The proposed heuristic is aimed at improving the overlapping time between the memory and the processor while keeping utilization balanced among cores. Energy savings depend on the range of frequency/voltage levels that DVS implements. Experimental results show that the proposed heuristic reduces the energy consumption in almost 3 times with respect to a system with no DVS regulator and applying no heuristic.