This article discusses the technological issues involved with continuing the miniaturization of dynamic random‐access memory cells into the gigabit era. Ever‐smaller giga‐generation dynamic random‐access memory cells require three‐dimensional high‐charge density capacitors with high‐e insulating films, leading to the need for further improvements in lithographic resolution for ever‐smaller, higher aspect ratio memory cells, and planarization technologies for reducing the memory‐cell height. This article demonstrates two technologies for meeting these two requirements: high acceleration energy electron‐beam lithography and KrF excimer‐laser phase‐shift photolithography, and plate‐wiring merge technology. Metal–insulator–metal 1.6 nm Ta2O5 CROWN capacitors and single Si3N4 spacer OSELO isolation technology for an experimental 1 Gbit dynamic random‐access memory chip are also discussed.