개선된 F함수 기반 ARIA 암호 알고리듬의 FPGA 설계

This paper presents the FPGA design of ARIA cipher algorithm based on improved F function. In conventional approach, three kinds of function are mainly used for substitution layer. In the proposed approach, an improved F function is introduced in such a way that three functions are merged into only one function for increasing the computation speed and reducing hardware overhead. The designed cryptosystem was described using Verilog HDL, and it was synthesized for a Xilinx VirtexE FPGA device, using the ISE 10.1 software tools. The cryptosystem operates at a clock frequency of 71 MHz with throughput of 652Mbps on Xilinx-VirtexE FPGA device.