New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity

Reconfigurability and low complexity are the two key requirements of finite impulse response (FIR) filters employed in multistandard wireless communication systems. In this paper, two new reconfigurable architectures of low complexity FIR filters are proposed, namely constant shifts method and programmable shifts method. The proposed FIR filter architecture is capable of operating for different wordlength filter coefficients without any overhead in the hardware circuitry. We show that dynamically reconfigurable filters can be efficiently implemented by using common subexpression elimination algorithms. The proposed architectures have been implemented and tested on Virtex 2v3000ff1152-4 field-programmable gate array and synthesized on 0.18 ¿m complementary metal-oxide-semiconductor technology with a precision of 16 bits. Design examples show that the proposed architectures offer good area and power reductions and speed improvement compared to the best existing reconfigurable FIR filter implementations in the literature.

[1]  N. Spencer.  An overview of digital telephony standards , 1998 .

[2]  A. Prasad Vinod,et al.  A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Ingrid Verbauwhede,et al.  Low power showdown: comparison of five DSP platforms implementing an LPC speech codec , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[4]  A. Prasad Vinod,et al.  On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Kam-Wing Ng,et al.  A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems , 2000, FPL.

[6]  R. Hartley.  Subexpression sharing in filters using canonic signed digit multipliers , 1996 .

[7]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Masato Motomura,et al.  A-combined approach to high-level synthesis for dynamically reconfigurable systems , 2004, IEEE Transactions on Computers.

[9]  In-Cheol Park,et al.  FIR filter synthesis algorithms for minimizing the delay and the number of adders , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Rainer Kress,et al.  High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems , 1998, FPL.

[11]  Patrick Schaumont,et al.  A new algorithm for elimination of common subexpressions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  K. Roy,et al.  Computation sharing programmable FIR filter for low-power and high-performance applications , 2004, IEEE Journal of Solid-State Circuits.

[13]  Chiang-Ju Chien,et al.  A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[14]  Ravinder David Koilpillai,et al.  Software radio issues in cellular base stations , 1999, IEEE J. Sel. Areas Commun..

[15]  Cid C. de Souza,et al.  Efficient datapath merging for partially reconfigurable architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  L. Wanhammar,et al.  Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm , 2002 .

[17]  I. Kale,et al.  Efficient implementation of digital filters using novel reconfigurable multiplier blocks , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[18]  O. Vainio,et al.  Comparison of programmable FIR filter architectures for low power , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[19]  Miodrag Potkonjak,et al.  Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Kaushik Roy,et al.  Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Joseph Mitola,et al.  Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering , 2000 .

[22]  In-Cheol Park,et al.  FIR filter synthesis algorithms for minimizing the delay and the number of adders , 2001 .

[23]  A. Prasad Vinod,et al.  Reconfigurable Low Complexity Fir Filters for Software Radio Receivers , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.

[24]  Robert A. Walker,et al.  A Survey of high-level synthesis systems , 1991 .

[25]  James C. Hoe,et al.  Time-Multiplexed Multiple-Constant Multiplication , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  A. Prasad Vinod,et al.  Low power and high-speed implementation of fir filters for software defined radio receivers , 2006, IEEE Transactions on Wireless Communications.

[27]  Tzi-Dar Chiueh,et al.  A Low-Power Digit-Based Reconfigurable FIR Filter , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[28]  Wang Hua,et al.  Design and implementation of a high-speed programmable polyphase FIR filter , 2003, ASICON 2003.

[29]  Achim Rettberg,et al.  Integration of Energy Reduction into High-Level Synthesis by Partitioning , 2006, DIPES.

[30]  A. Prasad Vinod,et al.  An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Michael Grüninger,et al.  Introduction , 2002, CACM.

[33]  Kaushik Roy,et al.  Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[34]  Jie Zhang,et al.  A high-speed, programmable, CSD coefficient FIR filter , 2002, IEEE Trans. Consumer Electron..

[35]  M Schaldach,et al.  [Design of digital filters]. , 1982, Biomedizinische Technik. Biomedical engineering.

[36]  Yair Linn,et al.  Efficient loop filter design in FPGAs for Phase Lock Loops in high-datarate wireless receivers — theory and case study , 2007, 2007 Wireless Telecommunications Symposium.

[37]  Jaroslav Krivánek,et al.  Implementation details , 2007, SIGGRAPH Courses.

[38]  Gerhard Fettweis,et al.  Software Radio Receivers , 1999 .