Design and Analysis of Power Distribution Networks in VLSI Circuits.

[1]  Saurabh Dighe,et al.  Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Paolo A. Aseron,et al.  On-Die Supply-Resonance Suppression Using Band-Limited Active Damping , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Makoto Nagata,et al.  Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Takayasu Sakurai,et al.  An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise , 2007, 2007 IEEE Symposium on VLSI Circuits.

[5]  C.H. Kim,et al.  A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping , 2007, 2007 IEEE Symposium on VLSI Circuits.

[6]  Y. Yasu,et al.  In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution , 2006, IEEE Journal of Solid-State Circuits.

[7]  Jieming Qi,et al.  A Circuit for Reducing Large Transient Current Effects on Processor Power Grids , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[8]  M. Celik,et al.  Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  Luciano Lavagno,et al.  Electronic Design Automation for Integrated Circuits Handbook , 2006 .

[10]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.

[11]  Yici Cai,et al.  Partitioning-based approach to fast on-chip decap budgeting and minimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Malgorzata Marek-Sadowska,et al.  Timing-aware power noise reduction in layout , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[13]  M. Nagata,et al.  A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits , 2005, IEEE Journal of Solid-State Circuits.

[14]  Tom Chen,et al.  Performance driven decoupling capacitor allocation considering data and clock interactions , 2005, Design, Automation and Test in Europe.

[15]  K. Ishibashi,et al.  An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs , 2004, IEEE Journal of Solid-State Circuits.

[16]  M. Horowitz,et al.  Circuits and techniques for high-resolution measurement of on-chip power supply noise , 2004, IEEE Journal of Solid-State Circuits.

[17]  Sani R. Nassif,et al.  Early-stage power grid analysis for uncertain working modes , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Eli Chiprout Fast flip-chip power grid analysis via locality and grid shells , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[19]  Eby G. Friedman,et al.  Impedance characteristics of power distribution grids in nanoscale integrated circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[21]  T. Rahal-Arabi,et al.  On-die droop detector for analog sensing of power supply noise , 2004, IEEE Journal of Solid-State Circuits.

[22]  F. Najm,et al.  Timing analysis in presence of power supply and ground voltage variations , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[23]  Sachin S. Sapatnekar,et al.  Analysis and optimization of structured power/ground networks , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Yu Zheng,et al.  On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[25]  Sani R. Nassif,et al.  Optimal decoupling capacitor sizing and placement for standard-cell layout designs , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Margaret Martonosi,et al.  Control techniques to eliminate voltage emergencies in high performance processors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[27]  David Blaauw,et al.  Inductance model and analysis methodology for high-speed on-chip interconnect , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[28]  Charlie Chung-Ping Chen,et al.  INDUCTWISE: inductance-wise interconnect simulator and extractor , 2002, ICCAD 2002.

[29]  Kaushik Roy,et al.  Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  M. Takamiya,et al.  An on-chip 100 GHz-sampling rate 8-channel sampling oscilloscope with embedded sampling clock generator , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[31]  Malgorzata Marek-Sadowska,et al.  Coping with buffer delay change due to power and ground noise , 2002, DAC '02.

[32]  Vivek Tiwari,et al.  Microarchitectural simulation and control of di/dt-induced power supply voltage variation , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[33]  A. E. Ruehii Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[34]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[35]  Shen Lin,et al.  Challenges in power-ground integrity , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[36]  Alberto L. Sangiovanni-Vincentelli,et al.  Techniques for including dielectrics when extracting passive low-order models of high speed interconnect , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[37]  Sudhakar Bobba,et al.  IC power distribution challenges , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[38]  Seth R. Sanders,et al.  An active clamp circuit for voltage regulation module (VRM) applications , 2001 .

[39]  A. Waizman,et al.  Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology , 2001 .

[40]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[41]  Min Xu,et al.  An efficient model for frequency-dependent on-chip inductance , 2001, GLSVLSI '01.

[42]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[43]  I. Hajj,et al.  RC power bus maximum voltage drop in digital VLSI circuits , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[44]  D. S. Wills,et al.  On-chip decoupling capacitor optimization using architectural level current signature prediction , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[45]  Rajendran Panda,et al.  Model and analysis for combined package and on-chip power grid simulation , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[46]  Atsushi Iwata,et al.  Measurements and analyses of substrate noise waveform inmixed-signal IC environment , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[47]  Resve A. Saleh,et al.  Clock skew verification in the presence of IR-drop in the powerdistribution network , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[49]  F. Herzel,et al.  Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[50]  A. Taylor,et al.  An on-chip voltage regulator using switched decoupling capacitors , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[51]  Rajendran Panda,et al.  Design and analysis of power distribution networks with accurate RLC models , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[52]  Kwang-Ting Cheng,et al.  VIP-an input pattern generator for identifying critical voltage drop for deep sub-micron designs , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[53]  P. Larsson Resonance and damping in CMOS circuits with on-chip decoupling capacitance , 1998 .

[54]  Ron Ho,et al.  Applications of on-chip samplers for test and measurement of integrated circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[55]  David Overhauser,et al.  Full-chip verification methods for DSM power distribution systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[56]  Rajendran Panda,et al.  Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.

[57]  A. Conn,et al.  Circuit optimization via adjoint Lagrangians , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[58]  S. R. Vemuru Effects of simultaneous switching noise on the tapered buffer design , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[59]  David D. Ling,et al.  Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.

[60]  Ibrahim N. Hajj,et al.  Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[61]  K. DeHaven,et al.  Controlled collapse chip connection (C4)-an enabling technology , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.

[62]  Mokhtar S. Bazaraa,et al.  Nonlinear Programming: Theory and Algorithms , 1993 .

[63]  Brian W. Kernighan,et al.  AMPL: A Modeling Language for Mathematical Programming , 1993 .

[64]  P. Toint,et al.  Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A) , 1992 .

[65]  S. Chowdhury,et al.  Estimation of maximum currents in MOS IC logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[66]  E. J. Rymaszewski,et al.  Microelectronics Packaging Handbook , 1988 .

[67]  William L. Briggs,et al.  A multigrid tutorial , 1987 .

[68]  Peter G. Doyle,et al.  Random Walks and Electric Networks: REFERENCES , 1987 .

[69]  G. Golub Matrix computations , 1983 .

[70]  Albert E. Ruehli,et al.  The modified nodal approach to network analysis , 1975 .

[71]  A. Ruehli Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[72]  J. Black Electromigration failure modes in aluminum metallization for semiconductor devices , 1969 .

[73]  R. Rohrer The Generalized Adjoint Network and Network Sensitivities , 1969 .