LCD Driver IC용 1T-SRAM의 Refresh 제어 회로 설계

In this paper, we propose a refresh control circuit for 1T-SRAM which is changeable with simple register settings keeping optimal area of memory cell due to variations of process characteristics or change of frame frequency. The main circuit consists of a reference clock generator which generates a reference clock determined by the size of optimal memory cell, a frame frequency clock generator which generates a frame clock by user setting, and a self refresh control which generates a refresh clock by comparing the reference clock to frame frequency clock. The proposed refresh control circuit has been designed in transistor level using 0.18㎛ CMOS technology library. Simulation results show that the frame clock frequency has 8.5㎐ ~ 132㎐ and refresh operation of 1T-RAM is well performed with even memory cell size 12fF and frame clock frequency 55㎐.