Development of FSM based Running Disparity Controlled 8b/10b Encoder/Decoder with Fast Error Detection Mechanism

T ransmitted bits have some certain characteristics which have effects on the error rate and the achievable bandwidth. This characteristic includes (1) ratio of 0’s and 1’s within a data byte and (2) maximum no. of clock periods between bit transitions (i.e. 1 -> 0 and vice versa). These characteristics are maintained and developed using an efficient encoder. Encoder increase the ability of a receiver performing clock recovery or deriving improved bit synchronization, helps distinguished control bit sequence and data ∗ASIC Design Engineer, Fastrack Anontex Limited Dhaka, Bangladesh. †ASIC Design Engineer, Fastrack Anontex Limited Dhaka, Bangladesh. ‡ASIC Design Engineer, Fastrack Anontex Limited Dhaka, Bangladesh. Abdullah-Al-Kafi et al. Development of FSM based Running Disparity Controlled 8b/10b Encoder/Decoder with Fast Error Detection Mechanism. Page 11 HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 2, March 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-111-6 bit sequences, allows simple detection of byte and word boundaries. In order to achieve DC balance serial data for faster clock recovery at receiver site this research gives a simple and practical solution for 8b/10b encoder/decoder. The Running Disparity method used here is FSM based and the two ROM look up tables have been made to accomplished perfect inversion. Besides we propose new method in error detection of 8b/10b encoder/decoder where k error detect the command code error in encoder, code error detect the invalid code input and RD error detect the running disparity error in decoder. The design while detecting error can hold the last correct running disparity until the correct running disparity input. On other whole, 10-bit for each 8-bit of data algorithm drops the data rate speed relative to line speed.