Three dimensional CMOS devices and integrated circuits

Three dimensional devices and, integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits.

[1]  M. Ieong,et al.  Examination of hole mobility in ultra-thin body SOI MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[2]  A. Chandrakasan,et al.  Design tools for 3-D integrated circuits , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[3]  G. G. Shahidi SOI technology for the GHz era , 2002, IBM J. Res. Dev..

[4]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5]  Vikas Agarwal,et al.  Clock rate versus IPC: the end of the road for conventional microarchitectures , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[6]  J. Treichler,et al.  Triple-self-aligned, planar double-gate MOSFETs: devices and circuits , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[7]  Kaushik Roy,et al.  Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits , 2001 .

[8]  T. Nigam,et al.  The vertical replacement-gate (VRG) MOSFET , 2002 .

[9]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[10]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[11]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[12]  Mansun Chan,et al.  Three dimensional CMOS integrated circuits on large grain polysilicon films , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[13]  K. Steinhubl Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[14]  R. Reif,et al.  Thermal analysis of three-dimensional (3-D) integrated circuits (ICs) , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[15]  B. Davari CMOS technology scaling, 0.1 /spl mu/m and beyond , 1996, International Electron Devices Meeting. Technical Digest.

[16]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[17]  Yoshinori Iida,et al.  Application of E-beam recrystallization to three-layer image processor fabrication , 1991 .

[18]  Donald E. Troxel,et al.  A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[19]  A. Rahman,et al.  Comparison of key performance metrics in two- and three-dimensional integrated circuits , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

[20]  Y. Uemoto,et al.  A high-performance stacked-CMOS SRAM cell by solid phase growth technique , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

[21]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[22]  Nicholas E. Brathwaite,et al.  Laminated memory: a new 3-dimensional packaging technology for MCMs , 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).

[23]  J. Kedzierski,et al.  Demonstration of FinFET CMOS circuits , 2002, 60th DRC. Conference Digest Device Research Conference.

[24]  Anna W. Topol,et al.  Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.

[25]  Bruce B. Doris,et al.  Ultra-thin Silicon Channel Single- and Double-gate MOSFETs , 2002 .

[26]  H.-S.P. Wong,et al.  Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[27]  A. Grill,et al.  Strained Si NMOSFETs for high performance CMOS technology , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[28]  W. Lai,et al.  The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[29]  S. Tiwari,et al.  Multi-layers with buried structures (MLBS): an approach to three-dimensional integration , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[30]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[31]  R. V. Joshi,et al.  3D Thermal Analysis for SOI and its impact on Circuit Performance , 2001 .

[32]  J. Kedzierski,et al.  A functional FinFET-DGCMOS SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[33]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[34]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[35]  Krishna C. Saraswat,et al.  High-performance germanium-seeded laterally crystallized TFTs for vertical device integration , 1998 .

[36]  S. Das,et al.  Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[37]  J.A. Davis,et al.  Interconnecting device opportunities for gigascale integration (GSI) , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).