A 0.35 /spl mu/m CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code

In this work, we present the design and preliminary testing results of the first reported CMOS analog turbo decoder for a code of realistic complexity, a parallel concatenated, rate 1/3, code defined in the 3GPP standard with interleaver size of 40 bits and a codeword size of 132 bits. The preliminary test results demonstrated a data rate of 2 Mbit/s, with a power consumption of 6.6 mW (decoder core alone) and an energy per decoded bit and trellis state of only 1.36 nJ. Different short range low power wireless data transmission systems for ISM (Industrial Scientific and Medical) applications are compared with respect to their performances (power consumption, distance range, architecture well suited to integration, etc).

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