A high speed scheduler/controller for unbuffered banyan networks
暂无分享,去创建一个
[1] Jonathan S. Turner,et al. Design of a gigabit ATM switch , 1997, Proceedings of INFOCOM '97.
[2] N. K. Sharma. Space and time redundant broadband packet switch , 1996, Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on Computers and Communications.
[3] Marc Snir,et al. The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.
[4] John A. Silvester,et al. A new parallel banyan ATM switch architecture , 1995, Proceedings IEEE International Conference on Communications ICC '95.
[5] Rami G. Melhem,et al. Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor , 1994, IEEE Trans. Parallel Distributed Syst..
[6] Achille Pattavina,et al. Analysis of replicated Banyan networks with input and output queueing for ATM switching , 1996, Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications.
[7] Fouad A. Tobagi,et al. Fast packet switch architectures for broadband integrated services digital networks , 1990, Proc. IEEE.
[8] Fouad A. Tobagi,et al. Architecture, Performance, and Implementation of the Tandem Banyan Fast Packet Switch , 1991, IEEE J. Sel. Areas Commun..
[9] Ramesh R. Rao,et al. Request Resubmission in a Blocking, Circuit-Switched, Interconnection Network , 1996, IEEE Trans. Computers.
[10] Nick McKeown,et al. The Tiny Tera: A Packet Switch Core , 1998, IEEE Micro.
[11] Ryuichi Watanabe,et al. Architecture of a packet switch based on banyan switching network with feedback loops , 1988, IEEE J. Sel. Areas Commun..
[12] K. L. Yeung. A new ATM switch design using wrapped around multiple (WAM) banyan network , 1995, Proceedings IEEE International Conference on Communications ICC '95.