시뮬레이션을 통한 TFET 소자에서의 Source-to-Gate Underlap/Overlap 길이에 따른 특성 변화 연구

Tunneling field effect transistor (TFET) has been investigated as a substitute for a conventional metal-oxide-semiconductor field effect transistor (MOSFET) in the field of low-power operation device. Especially, the vertical TFET has been studied because it has high denity and merit for fabrication. In this paper, the source -to-gate underlap/overlap - dependent characteristic of TFET arising from a gate etch process in vertical TFET is investigated through a technology computer aided design (TCAD) simulation.