Novel Prediction Framework for Path Delay Variation Based on Learning Method
暂无分享,去创建一个
[1] Massimo Alioto,et al. Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[2] Jan M. Rabaey,et al. Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.
[3] Hidetoshi Onodera,et al. Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization , 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..
[4] Alessandro Trifiletti,et al. A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] Zeev Zalevsky,et al. Improving Raman spectra of pure silicon using super-resolved method , 2019, Journal of Optics.
[6] Mohab Anis,et al. A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] M. D. Giles,et al. Process Technology Variation , 2011, IEEE Transactions on Electron Devices.
[8] Jianqiang Yi,et al. BP neural network prediction-based variable-period sampling approach for networked control systems , 2007, Appl. Math. Comput..
[9] Yiyu Shi,et al. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Ankur Srivastava,et al. A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] David Blaauw,et al. Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.
[12] Wei Ge,et al. Analytical inverter chain's delay and its variation model for sub-threshold circuits , 2017, IEICE Electron. Express.
[13] Marco Lanuzza,et al. Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[14] Zeev Zalevsky,et al. Improved Diagnostic Process of Multiple Sclerosis Using Automated Detection and Selection Process in Magnetic Resonance Imaging , 2017 .
[15] Stefania Perri,et al. Analytical Delay Model Considering Variability Effects in Subthreshold Domain , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.
[16] Witold Pedrycz,et al. Automatic Selection of Process Corner Simulations for Faster Design Verification , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] David Money Harris,et al. A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] Takayasu Sakurai,et al. Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.
[19] Yang Xu,et al. On Timing Model Extraction and Hierarchical Statistical Timing Analysis , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] H. S. Jamadagni,et al. Voltage and Temperature-Aware SSTA Using Neural Network Delay Model , 2011, IEEE Transactions on Semiconductor Manufacturing.
[21] Zeev Zalevsky,et al. Neural networks within multi-core optic fibers , 2016, Scientific Reports.