A receiver IC for a 1 + 1 digital transmission system is presented. It includes all the functions necessary for data recovery (high-pass filtering, automatic gain control (AGC), clock extraction, decision circuitry) and for supplying the control code to a separately integrated echo canceller. A total switched-capacitor (SC) approach with digital control is used and a complete description of the receiver architecture is given. The techniques for combatting errors introduced in the analog domain by clock feedthrough and digital crosstalk are described. A special purpose program is described which simulates the whole receiver and overcomes the problems arising from the mixed sampled data/digital nature of the design. The IC has been fabricated in a 3- /spl mu/m p-well CMOS process.
[1]
R. Gregorian,et al.
Switched-capacitor circuit design
,
1983,
Proceedings of the IEEE.
[2]
R. Gregorian.
Switched-capacitor filter design using cascaded sections
,
1980
.
[3]
P.R. Gray,et al.
A MOS switched-capacitor instrumentation amplifier
,
1982,
IEEE Journal of Solid-State Circuits.
[4]
K. W. Martin.
New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuits
,
1982
.
[5]
K. Martin,et al.
Exact design of switched-capacitor bandpass filters using coupled-biquad structures
,
1980
.