On-chip testing techniques for RF wireless transceiver systems and components

The combination of a switched loop-back architecture with the use of the recently developed on-chip testing devices demonstrated in integrated implementations significantly enhances the testability of an RF transceiver. The on-chip testing devices show that the direct, on-chip observation of analogue and RF building blocks at megahertz and gigahertz frequencies can be performed in a CMOS process, and with a minimum area and parasitic loading overhead. The presented strategy enables the test of the entire wireless system and its individual building blocks at the wafer level through digital information. The use of external analogue/RF equipment or components is avoided, allowing the implementation of a practical and cost-effective test solution. Extending the proposed concepts to implementations in current deep submicron technologies opens significant opportunities for improved performance as well as the solution to new challenges.