Jason Wei

Label Noise Reduction Without Assumptions

Jason Wei, Jason Wei, 2020 .

A 25GHz 100ns lock time digital LC PLL with an 8-phase output clock

Jason Wei, Mohammad Hekmat, Reza Navid, 2013, 2013 Symposium on VLSI Circuits.

Text Augmentation in a Multi-Task View pdf

Soroush Vosoughi, Jason Wei, Chengyu Huang, 2021, ArXiv.

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

An Empirical Survey of Unsupervised Text Representation Methods on Twitter Data pdf

Soroush Vosoughi, Weicheng Ma, Ruibo Liu, 2020, WNUT.

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

Masum Hossain, Jared Zerbe, Barry Daly, 2014, IEEE Journal of Solid-State Circuits.

Design challenges for high performance and power efficient graphics and mobile memory interfaces

Amir Amirkhany, Brian Leibowitz, Chuck Yuan, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

Jason Wei, Mohammad Hekmat, Reza Navid, 2015, IEEE Journal of Solid-State Circuits.

A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface

Jared Zerbe, Barry Daly, John Eble, 2013, 2013 Symposium on VLSI Circuits.

Few-Shot Text Classification with Triplet Networks, Data Augmentation, and Curriculum Learning

Soroush Vosoughi, Jason Wei, Yu Cheng, 2021, NAACL.