H. C. Srinivasaiah

发表

Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length

M C Parameshwara, H. C. Srinivasaiah, 2015 .

Design of DTS for Clustered Wireless Sensor Networks

H. C. Srinivasaiah, Naveen Urs, 2014 .

Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs

H. C. Srinivasaiah, K. S. Shashidhara, 2019 .

Design of Multiband Microstrip Dipole Antenna for LTE, GSM, UMTS, LORA and WLAN Applications

H. C. Srinivasaiah, S Mamatha., 2019 .

A Novel Low Power 1-bit Full Adder with CMOS Transmission-gate Architecture for Portable Applications

H. C. Srinivasaiah, M. C. Parameshwara, K. S. Shashidhara, 2013 .

Implant dose sensitivity of 0.1 /spl mu/m CMOS inverter delay

Navakanta Bhat, H. C. Srinivasaiah, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations

Navakanta Bhat, H. C. Srinivasaiah, N. Bhat, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Study of SRAM Cell for Balancing Read and Write Margins in Sub-100nm Technology using Noise-Curve Method

H. C. Srinivasaiah, G Malleshaiah, 2015 .

Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM

H. C. Srinivasaiah, 2012, 2012 25th International Conference on VLSI Design.

Hardware co-simulation of 1024-point FFT and it's Implementation, in Simulink, Xilinx Vivado IDE on Zynq-7000 FPGA

H. C. Srinivasaiah, K. S. Shashidhara, 2019 .

Monte Carlo analysis of the implant dose sensitivity in 0.1 μm NMOSFET

Navakanta Bhat, H. C. Srinivasaiah, N. Bhat, 2003 .

Response surface modeling of 100 nm CMOS process technology using design of experiment

Navakanta Bhat, H. C. Srinivasaiah, N. Bhat, 2004, 17th International Conference on VLSI Design. Proceedings..

Empirical Model Based Variability Analysis of Terminal Currents of MOSFET of a 65nm SRAM Cell in Process-Voltage-Temperature (PVT) Space

H. C. Srinivasaiah, G Malleshaiah, C Parameshwara.M., 2014 .

Choice of Adders for Multimedia Processing Applications: Comparison of Various Existing and a Novel 1-Bit Full Adder

Iosr journals, H. C. Srinivasaiah, C ParameshwaraM., 2015 .

Techniques For Detection Of Analog TV Whitespace In Electromagnetic Spectrum For Cognitive Radio Applications

H. C. Srinivasaiah, Arun. A. Badiger, 2013 .

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

H. C. Srinivasaiah, M. C. Parameshwara, 2017, J. Circuits Syst. Comput..

A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

H. C. Srinivasaiah, G. Malleshaiah, 2018, European Journal of Engineering Research and Science.

Study of spectral purity dependence on sine-ROM size in a digitally controlled frequency synthesizer

H. C. Srinivasaiah, M. C. Parameshwara, 2017, 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

Characterization of sub-100 nm CMOS process using screening experiment technique

H. C. Srinivasaiah, N. Bhat, 2005 .

Low power and area efficient FFT architecture through decomposition technique

H. C. Srinivasaiah, K. S. Shashidhara, K. S. Shashidhara, 2017, 2017 International Conference on Computer Communication and Informatics (ICCCI).