Chung-Kuan Cheng

发表

A probabilistic multicommodity-flow solution to circuit clustering problems

C. Yeh, Chung-Kuan Cheng, T.-T.Y. Lin, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Circuit partitioning and its applications to vlsi designs

Yen-Chuen A. Wei, Chung-Kuan Cheng, 1990 .

Clock Skew Analysis via Vector Fitting in Frequency Domain

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2005, 2005 International Conference on Computer Design.

An improved two-way partitioning algorithm with stable performance [VLSI]

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Towards efficient hierarchical designs by ratio cut partitioning

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Skew sensitivity minimization of buffered clock tree

Jae Chung, Chung-Kuan Cheng, Chung-Kuan Cheng, 1994, ICCAD '94.

Wire Length And Delay Minimization In General Clock Net Routing

Chung-Kuan Cheng, N. Chou, Nan-Chi Chou, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Solving the Net Matching Pro erforrnance Chip Desi

Chung-Kuan Cheng, Ramamohan Paturi, Masahiro Fujita, 1996 .

A wire length estimation technique utilizing neighborhood density equations

Chung-Kuan Cheng, P. Chau, T. Hamada, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Developing an EEG-based on-line closed-loop lapse detection and mitigation system

T. Jung, Chung-Kuan Cheng, Yu-Te Wang, 2014, Front. Neurosci..

RCLK-VJ network reduction with Hurwitz polynomial approximation

Chung-Kuan Cheng, Zhanhai Qin, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Data flow partitioning with clock period and latency constraints

Chung-Kuan Cheng, J. Lillis, M. Shih, 1997 .

The optimal circuit decompositions using network flow formulations

Chung-Kuan Cheng, 1990, IEEE International Symposium on Circuits and Systems.

Ratio of the Worst Case Noise and the Impedance of Power Distribution Network

Chung-Kuan Cheng, X. Zhang, Yang Liu, 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Minimizing the worst-case voltage noise for power distribution network using time-varying equivalent serial resistance

Chung-Kuan Cheng, X. Zhang, Yang Liu, 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

Clock Skew Analysis via Vector Fitting in Frequency Domain

Wenjian Yu, Chung-Kuan Cheng, Haikun Zhu, 2008, ISQED 2008.

Dynamic analysis of power delivery network with nonlinear components using matrix exponential method

Chung-Kuan Cheng, Hao Zhuang, Ilgweon Kang, 2015, 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity.

MEG Working Memory N-Back Task Reveals Functional Deficits in Combat-Related Mild Traumatic Brain Injury.

Roland R. Lee, Charles W. Huang, Chung-Kuan Cheng, 2019, Cerebral cortex.

Marked Increases in Resting-State MEG Gamma-Band Activity in Combat-Related Mild Traumatic Brain Injury.

Roland R. Lee, Charles W. Huang, Chung-Kuan Cheng, 2020, Cerebral cortex.

Eecient Boolean Division and Substitution

D. I. Cheng, Chung-Kuan Cheng, Shih-Chieh Chang, 1998 .

Optimal planning for mesh-based power distribution

A. Kahng, Chung-Kuan Cheng, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Boosting off-chip interconnects through chip-to-chip capacitive coupled communication

Chung-Kuan Cheng, X. Zhang, Dongwon Park, 2017, 2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Two-stage newton–raphson method for transistor-level simulation

Chung-Kuan Cheng, E. Kuh, Zhengyong Zhu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation

Chung-Kuan Cheng, W. Ku, Xiaodong Yang, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Integrated algorithmic logical and physical design of integer multiplier

Chung-Kuan Cheng, Shuo Zhou, B. Yao, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility

Chung-Kuan Cheng, Daeyeal Lee, Dong-won Park, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

The Y-architecture for on-chip interconnect: analysis and methodology

A. Kahng, Chung-Kuan Cheng, I. Măndoiu, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Electrical Engineering (Computer Engineering)

Tajana Rosing, Lawrence E. Larson, Chung-Kuan Cheng, 2008 .

Floorplan and placement approaches for vlsi physical design

Chung-Kuan Cheng, Pei-Ning Guo, Chung-Kuan Cheng, 1998 .

Analyzing High-Density ECG Signals Using ICA

Tzyy-Ping Jung, Yi Zhu, Chung-Kuan Cheng, 2008, IEEE Transactions on Biomedical Engineering.

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Chung-Kuan Cheng, J. Lillis, Ting-Ting Y. Lin, 1996, 33rd Design Automation Conference Proceedings, 1996.

Timing optimization for multi-source nets

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1997, DAC 1997.

An unconditional stable general operator splitting method for transistor level

Chung-Kuan Cheng, Ernest S. Kuh, Zhengyong Zhu, 2006 .

Power network analysis using an adaptive algebraic multigrid approach

Chung-Kuan Cheng, Zhengyong Zhu, B. Yao, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Buffer planning algorithm based on partial clustered floorplanning

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, Sixth international symposium on quality electronic design (isqed'05).

VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation

Chung-Kuan Cheng, Sheqin Dong, Yici Cai, 2001 .

Efficient transient simulation for transistor-level analysis

Chung-Kuan Cheng, Ernest S. Kuh, Manjit Borah, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Area efficient pipelined pseudo-exhaustive testing with retiming

Chung-Kuan Cheng, Huoy-Yu Liou, Ting-Ting Y. Lin, 1996, 33rd Design Automation Conference Proceedings, 1996.

PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes

Andrew B. Kahng, Hayoung Kim, Chung-Kuan Cheng, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Network Flow Approach For Hierarchical Tree Partitioning

Chung-Kuan Cheng, M. Kuo, 1997, Proceedings of the 34th Design Automation Conference.

An algorithmic approach for generic parallel adders

Chung-Kuan Cheng, Haikun Zhu, Shuo Zhou, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Performance driven multiple-source bus synthesis using buffer insertion

Chung-Kuan Cheng, Chia-Chun Tsai, Ting-Ting Y. Lin, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Toward better wireload models in the presence of obstacles

A. Kahng, Chung-Kuan Cheng, D. Stroobandt, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

An O-tree representation of non-slicing floorplan and its applications

Chung-Kuan Cheng, T. Yoshimura, Pei-Ning Guo, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

A a Theoretical al Solutio

Chung-Kuan Cheng, Robert C. Cas-den, Jianmin Li, 1996 .

Title A fast time-domain EM-TCAD coupled simulation framework viamatrix exponential

Chung-Kuan Cheng, Guanhua Chen, Lijun Jiang, 2012 .

SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes

Hayoung Kim, Dong-won Park, Bill Lin, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Monolithic 3D Semiconductor Footprint Scaling Exploration based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Chung-Kuan Cheng, Daeyeal Lee, Bill Lin, 2022, IEEE Access.

Title Circuit simulation via matrix exponential method for stiffnesshandling and parallel processing

Chung-Kuan Cheng, Quan Chen, N. Wong, 2012 .

Layer Minimization of Escape Routing in Area Array Packaging

Rui Shi, Chung-Kuan Cheng, Renshen Wang, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Constructing Zero-deficiency Parallel Prefix Circuits of Minimum Depth

Chung-Kuan Cheng, Haikun Zhu, R. Graham, 2005 .

ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method

Chung-Kuan Cheng, Chin-Chih Chang, Chin-Chi Teng, 2015, TODE.

ePlace-3D: Electrostatics based Placement for 3D-ICs

Chung-Kuan Cheng, Hao Zhuang, Pengwen Chen, 2015, ISPD.

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Chung-Kuan Cheng, Hongliang Chang, Hao Zhuang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ePlace: Electrostatics based placement using Nesterov's method

Chung-Kuan Cheng, Chin-Chih Chang, Chin-Chi Teng, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

A hierarchical three-way interconnect architecture for hexagonal processors

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2003, SLIP '03.

CMOS Power Amplifiers for Wireless Communications

Peter M. Asbeck, Chung-Kuan Cheng, Lawrence E. Larson, 2003 .

Noninvasive Study of the Human Heart using Independent Component Analysis

Tzyy-Ping Jung, Yi Zhu, Chung-Kuan Cheng, 2006, Sixth IEEE Symposium on BioInformatics and BioEngineering (BIBE'06).

Ratio cut partitioning for hierarchical designs

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Epidermal Graphene Sensors and Machine Learning for Estimating Swallowed Volume

Laura L. Becerra, Chung-Kuan Cheng, P. Mercier, 2021, ACS Applied Nano Materials.

Timing optimization for multisource nets: characterization andoptimal repeater insertion

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

TIGER: an efficient timing-driven global router for gate array and standard cell layout design

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal wire sizing and buffer insertion for low power and a generalized delay model

Chung-Kuan Cheng, John Lillis, T.-T.Y. Lin, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Tiger: a timing-driven gate array and standard cell layout system

Xianlong Hong, Ernest S. Kuh, Chung-Kuan Cheng, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

Interconnect and output driver modeling of high speed designs

Chung-Kuan Cheng, Xrao-Ming Xiong, Chung-Kuan Cheng, 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.

PAS: A stand alone placement annotation system for high speed designs

Chung-Kuan Cheng, Xiao-Ming Xiong, J. Hardin, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Parallel transistor level circuit simulation using domain decomposition methods

Chung-Kuan Cheng, He Peng, Chung-Kuan Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

Worst-case performance prediction under supply voltage and temperature variation

Andrew B. Kahng, Chung-Kuan Cheng, Kambiz Samadi, 2010, SLIP '10.

Reconfigurable Computing

Philip H. W. Leong, A. Kahng, Chung-Kuan Cheng, 2017 .

Balancing the interconnect topology for arrays of processors between cost and power

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

The Orientation of Modules Based on Graph Decomposition

Chung-Kuan Cheng, T. C. Hu, So-Zen Yao, 1991, IEEE Trans. Computers.

Performance driven bus buffer insertion

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Exploring Cardioneural Signals from Noninvasive ECG Measurement

Yi Zhu, Chung-Kuan Cheng, Amirali Shayan Arani, 2007, 2007 IEEE 7th International Symposium on BioInformatics and BioEngineering.

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

Low power passive equalizer optimization using tritonic step response

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Tree Structures and Algorithms for Physical Design

Ronald L. Graham, Chung-Kuan Cheng, Dongwon Park, 2018, ISPD.

Resting‐state magnetoencephalography source magnitude imaging with deep‐learning neural network for classification of symptomatic combat‐related mild traumatic brain injury

Roland R. Lee, Charles W. Huang, Chung-Kuan Cheng, 2021, Human brain mapping.

Cell-phone based Drowsiness Monitoring and Management system

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

High-speed and low-power on-chip global link using continuous-time linear equalizer

Chung-Kuan Cheng, James F. Buckwalter, Yulei Zhang, 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network

He Peng, Wenjian Yu, Xiaoming Chen, 2009, 2009 10th International Symposium on Quality Electronic Design.

Hurwitz stable reduced order modeling for RLC interconnect trees

Chung-Kuan Cheng, Xiaodong Yang, Walter H. Ku, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

FARM: an efficient feed-through pin assignment algorithm

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Timing Optimization For Multi-source Nets: Characterization And Optimal Repeater Insertion

Chung-Kuan Cheng, J. Lillis, Chung-Kuan Cheng, 1997, Proceedings of the 34th Design Automation Conference.

Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

An Online Brain-Computer Interface Based on SSVEPs Measured From Non-Hair-Bearing Areas

Tzyy-Ping Jung, Chun-Shu Wei, Yijun Wang, 2017, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Eye prediction of digital driver with power distribution network noise

Tzong-Lin Wu, Chung-Kuan Cheng, Chiu-Chih Chou, 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2010, ISPD '10.

Maximum concurrent flows and minimum cuts

Chung-Kuan Cheng, T. C. Hu, Chung-Kuan Cheng, 1992, Algorithmica.

Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing

Chung-Kuan Cheng, Lung-Tien Liu, Ting-Ting Lin, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

From Circuit Theory, Simulation to SPICEDiego<\/sup>: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits

Chung-Kuan Cheng, Quan Chen, Xinyuan Wang, 2016, IEEE Circuits and Systems Magazine.

An algorithmic framework for efficient large-scale circuit simulation using exponential integrators

Wenjian Yu, Chung-Kuan Cheng, Hao Zhuang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Realizable parasitic reduction using generalized Y-Δ transformation

Chung-Kuan Cheng, Zhanhai Qin, Chung-Kuan Cheng, 2003, DAC.

Realizable parasitic reduction using generalized Y-/spl Delta/ transformation

Chung-Kuan Cheng, Zhanhai Qin, Chung-Kuan Cheng, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

A general purpose multiple way partitioning algorithm

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1991, 28th ACM/IEEE Design Automation Conference.

Tutorial on VLSI Partitioning

Chung-Kuan Cheng, Sao-Jie Chen, Chung-Kuan Cheng, 2000, VLSI Design.

Design considerations and algorithms for partitioning optoelectronic multichip modules.

Volkan H. Ozguz, Brian Catanzaro, Sing H. Lee, 1995, Applied optics.

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Andrew B. Kahng, Chung-Kuan Cheng, Ilgweon Kang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints

Ngai Wong, Xiang Hu, Chung-Kuan Cheng, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing

Chung-Kuan Cheng, Po-Ya Hsu, Chung-Kuan Cheng, 2020, 2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC).

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2018, ACM Trans. Design Autom. Electr. Syst..

Semi-Supervised Laplacian Learning on Stiefel Manifolds

Chung-Kuan Cheng, Pengwen Chen, A. Cloninger, 2023, ArXiv.

Ancestor tree for arbitrary multi-terminal cut functions

Chung-Kuan Cheng, T. C. Hu, Chung-Kuan Cheng, 1990, IPCO.

Circuit clustering using a stochastic flow injection method

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A two-level two-way partitioning algorithm

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Linear placement algorithms and applications to VLSI design

Chung-Kuan Cheng, Chung-Kuan Cheng, 1987, Networks.

A block-diagonal structured model reduction scheme for power grid networks

Ngai Wong, Xiang Hu, Chung-Kuan Cheng, 2011, 2011 Design, Automation & Test in Europe.

DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs

A. Kahng, Chung-Kuan Cheng, Bill Lin, 2022, ACM Trans. Design Autom. Electr. Syst..

Impulse response generation from S-parameters for power delivery network simulation

Chung-Kuan Cheng, Ilgweon Kang, Xinan Wang, 2015, 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity.

Floorplanning using a tree representation

Takeshi Yoshimura, Chung-Kuan Cheng, Toshihiko Takahashi, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Network partitioning into tree hierarchies

Chung-Kuan Cheng, Lung-Tien Liu, M. Kuo, 1996, Design Automation Conference, Proceedings.

Circuit Partitioning for Huge Logic Emulation Systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1994, 31st Design Automation Conference.

Empirical Study of Block Placement by Cluster Refinement

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1999, VLSI Design.

A gradient method on the initial partition of Fiduccia-Mattheyses algorithm

Chung-Kuan Cheng, Lung-Tien Liu, L.-T. Liu, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP

Chi-Yuan Lo, So-Zen Yao, Debaprosad Dutt, 1993, 30th ACM/IEEE Design Automation Conference.

GRA-LPO: Graph Convolution Based Leakage Power Optimization

Chung-Kuan Cheng, Uday Mallappa, Chung-Kuan Cheng, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Assessment of Reinforcement Learning for Macro Placement

A. Kahng, Chung-Kuan Cheng, Zhiang Wang, 2023, ISPD.

A mulitple level network approach for clock skew minimization with process variations

Chung-Kuan Cheng, Bo Yao, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards

Yi Zhu, Thomas Weng, Chung-Kuan Cheng, 2009, IEEE Transactions on Education.

Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation

Chung-Kuan Cheng, Xinyuan Wang, Hao Zhuang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Power grid simulation using matrix exponential method with rational Krylov subspaces

Chung-Kuan Cheng, Hao Zhuang, Shih-Hung Weng, 2013, 2013 IEEE 10th International Conference on ASIC.

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques

Chung-Kuan Cheng, Bill Lin, Sicun Gao, 2019, ISPD.

Fast and Precise Routability Analysis with Conditional Design Rules

Chung-Kuan Cheng, Dongwon Park, Ilgweon Kang, 2018, 2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

VLSI floorplanning with boundary constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs

Devon J. Merrill, Chung-Kuan Cheng, Ting-Chou Lin, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT

Chung-Kuan Cheng, Bill Lin, Chia-Tung Ho, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Timing-power optimization for mixed-radix Ling adders by integer linear programming

Yi Zhu, Jianhua Liu, Chung-Kuan Cheng, 2008, 2008 Asia and South Pacific Design Automation Conference.

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

Jianhua Liu, Chung-Kuan Cheng, John Lillis, 2007, 2007 Asia and South Pacific Design Automation Conference.

Block placement with symmetry constraints based on the O-tree non-slicing representation

Chung-Kuan Cheng, Florin Balasa, Koen Lampaert, 2000, DAC.

Floorplan representations: Complexity and connections

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2003, TODE.

Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning

Chung-Kuan Cheng, Bill Lin, Chester Holtz, 2021, 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

3-D floorplanning using labeled tree and dual sequences

Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, 2008, ISPD '08.

Fast evaluation of Bounded Slice-line Grid

Jun Gu, Sheqin Dong, Xianlong Hong, 2004, Journal of Computer Science and Technology.

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Evaluating a bounded slice-line grid assignment in O(nlogn) time

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An enhanced perturbing algorithm for floorplan design using the O-tree representation

Takeshi Yoshimura, Chung-Kuan Cheng, Yingxin Pang, 2000, ISPD '00.

Simple tree-construction heuristics for the fanout problem

Masahiro Fujita, Chung-Kuan Cheng, Robert J. Carragher, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Skew Sensitivity Minimization Of Buffered Clock Tree

Chung-Kuan Cheng, Jae Chung, Chung-Kuan Cheng, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Qiang Zhou, Zhuoyuan Li, Vijay Pitchumani, 2006, ISPD '06.

The optimal partitioning of networks

Chung-Kuan Cheng, Chung-Kuan Cheng, 1992, Networks.

Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links

Wenjian Yu, Yulei Zhang, Chung-Kuan Cheng, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Low Power Passive Equalizer Design for Computer Memory Links

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

Sequence-pair approach for rectilinear module placement

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Revisiting floorplan representations

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2001, ISPD '01.

Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks

Xiang Zhang, Wenjian Yu, Ilgweon Kang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MATEX: A distributed framework for transient simulation of power distribution networks

Chung-Kuan Cheng, Hao Zhuang, Shih-Hung Weng, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Multiple-level partitioning: an application to the very large-scale hardware simulator

Chung-Kuan Cheng, Y.-C. Wei, Z. Wurman, 1991 .

Application Multiple-Level Partitioning: An the Very Large-scale Hardware Simulator

Chung-Kuan Cheng, Yen-Chuen A. Wei, Yen-Chuen Wei, 1991 .

Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction

Feng Zhou, Chung-Kuan Cheng, Hongyu Chen, 2002, SLIP '02.

An Efficient Timing-Driven Global Routing Algorithm

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1993, 30th ACM/IEEE Design Automation Conference.

Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach

Chung-Kuan Cheng, Paul M. Chau, Takeo Hamada, 1993, 30th ACM/IEEE Design Automation Conference.

Algorithms for performance-driven design of integrated circuits

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1996 .

A global router with a theoretical bound on the optimal solution

Chung-Kuan Cheng, Jianmin Li, IV RobertC.Carden, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Linear decomposition algorithm for VLSI design applications

Chung-Kuan Cheng, John Lillis, Jianmin Li, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Satoshi Goto, Sheqin Dong, Chung-Kuan Cheng, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Yici Cai, Qiang Zhou, Zhuoyuan Li, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Performance constrained floorplanning based on partial clustering [IC layout]

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Corner block list representation and its application with boundary constraints

Yici Cai, Jun Gu, Sheqin Dong, 2004, Science in China Series F: Information Sciences.

Arbitrary convex and concave rectilinear block packing based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An optimum placement search algorithm based on extended Corner Block List

Yici Cai, Jun Gu, Shuo Zhou, 2002, Journal of Computer Science and Technology.

Module placement with boundary constraints using O-tree representation

Yici Cai, Jun Gu, Sheqin Dong, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Stairway compaction using corner block list and its applications with rectilinear blocks

Yici Cai, Jun Gu, Sheqin Dong, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Floorplanning with abutment constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Integr..

A compact algorithm for placement design using corner block list representation

Jun Gu, Sheqin Dong, Xianlong Hong, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, DAC '01.

ECBL: an extended corner block list with solution space including optimum placement

Jun Gu, Shuo Zhou, Sheqin Dong, 2001, ISPD '01.

A non-slicing floorplanning algorithm using corner block list topological representation

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

3D floorplan representations: Corner links and partial order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

Chung-Kuan Cheng, Hao Zhuang, Kambiz Samadi, 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph

Andrew B. Kahng, Chung-Kuan Cheng, Peng Du, 2012, ISPD '12.

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning

Qiang Zhou, Zhuoyuan Li, Wenjian Yu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer

Po-Ya Hsu, Anushka Gupta, Eric Chang, 2019, 2019 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Tree Structures and Algorithms for Physical Design

Chung-Kuan Cheng, Ilgweon Kang, Dongwon Park, 2018, ISPD.

A fast time‐domain EM–TCAD coupled simulation framework via matrix exponential with stiffness reduction

Quan Chen, Ngai Wong, Chung-Kuan Cheng, 2016, Int. J. Circuit Theory Appl..

A fast time-domain EM-TCAD coupled simulation framework via matrix exponential

Quan Chen, Lijun Jiang, Ngai Wong, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FPGA global routing architecture optimization using a multicommodity flow approach

Yi Zhu, Chung-Kuan Cheng, Michael Bedford Taylor, 2007, 2007 25th International Conference on Computer Design.

Energy and switch area optimizations for FPGA global routing architectures

Yi Zhu, Chung-Kuan Cheng, Michael Bedford Taylor, 2009, TODE.

An iterative division algorithm for FPGAs

Jianhua Liu, Chung-Kuan Cheng, Michael Chang, 2006, FPGA '06.

A global router using an efficient approximate multicommodity multiterminal flow algorithm

IV RobertC.Carden, Chung-Kuan Cheng, Chung-Kuan Cheng, 1991, 28th ACM/IEEE Design Automation Conference.

New spectral linear placement and clustering approach

Chung-Kuan Cheng, Lung-Tien Liu, John Lillis, 1996, 33rd Design Automation Conference Proceedings, 1996.

Linear decomposition algorithm for VLSI design applications

Chung-Kuan Cheng, J. Lillis, Jianmin Li, 1995, International Conference on Computer Aided Design.

Module Placement Based on Resistive Network Optimization

Chung-Kuan Cheng, Ernest S. Kuh, Chung-Kuan Cheng, 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Takumi Okamoto, Chung-Kuan Cheng, Renshen Wang, 2009, 2009 IEEE International Conference on Computer Design.

Octilinear redistributive routing in bump arrays

Chung-Kuan Cheng, Renshen Wang, Chung-Kuan Cheng, 2009, GLSVLSI '09.

Local ratio cut and set covering partitioning for huge logic emulation systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance-Driven Partitioning Using a Replication Graph Approach

Chung-Kuan Cheng, T. C. Hu, Lung-Tien Liu, 1995, 32nd Design Automation Conference.