David G. Chinnery

发表

Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design

David G. Chinnery, Kurt Keutzer, K. Keutzer, 2002 .

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach

David G. Chinnery, Chris C. N. Chu, Ankur Sharma, 2019, ISPD.

A functional validation technique: biased-random simulation guided by observability-based coverage

David G. Chinnery, Kurt Keutzer, Serdar Tasiran, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Achieving 550 MHz in an ASIC methodology

David G. Chinnery, Kurt Keutzer, Borivoje Nikolic, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

David G. Chinnery, Kurt Keutzer, Michael Orshansky, 2003, ISLPED '03.

Closing the power gap between ASIC and custom: an ASIC perspective

David G. Chinnery, Kurt Keutzer, K. Keutzer, 2000, Proceedings. 42nd Design Automation Conference, 2005..

Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design

David G. Chinnery, Kurt Keutzer, 2005 .

High performance and low power design techniques for ASIC and custom in nanometer technologies

David G. Chinnery, D. Chinnery, 2013, ISPD '13.

Rapid gate sizing with fewer iterations of Lagrangian Relaxation

David G. Chinnery, Chris C. N. Chu, Ankur Sharma, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Closing the gap between ASIC and custom: an ASIC perspective

David G. Chinnery, Kurt Keutzer, K. Keutzer, 2000, Proceedings 37th Design Automation Conference.

Timing driven incremental multi-bit register composition using a placement-aware ILP formulation

David G. Chinnery, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Fast Lagrangian Relaxation based gate sizing using multi-threading

David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Low power multiplication algorithm for switching activity reduction through operand decomposition

David G. Chinnery, Kurt Keutzer, Masayuki Ito, 2003, Proceedings 21st International Conference on Computer Design.

Session details: Detailed Routing Contest Results

David G. Chinnery, D. Chinnery, 2019, ACM International Symposium on Physical Design.

Linear programming for sizing, Vth and Vdd assignment

David G. Chinnery, Kurt Keutzer, K. Keutzer, 2005, ISLPED '05.