T. J. Chin

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

Low-skew clock distribution using zero-phase-clock-buffer DLLs

Ting Wu, Ken Chang, Carl W. Werner, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Clocking circuits for a 16Gb/s memory interface

Ting Wu, Jung-Hoon Chun, Ken Chang, 2008, 2008 IEEE Custom Integrated Circuits Conference.