Dave Secker

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

Effects of plating stubs on the electrical performance of wirebond PBGA packages

Chuck Yuan, Wendemagegnehu T. Beyene, Dave Secker, 2002 .

Measurement and characterization of backplanes for serial links operating at 56 Gbps

Wendemagegnehu T. Beyene, Yeon-Chang Hahm, Dave Secker, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Design of low cost QFP packages for multi-gigabit memory interface

Yi Lu, Dan Oh, Joong-Ho Kim, 2009, 2009 59th Electronic Components and Technology Conference.

Lessons learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Jihong Ren, Yeon-Chang Hahm, Dave Secker, 2014 .

On overcoming the limitations of single-ended signaling for graphics memory interfaces

Aliazam Abbasfar, Amir Amirkhany, Dan Oh, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

Wendemagegnehu Beyene, Dave Secker, Yuriy Shlepnev, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).