Vijay Khawshe

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link

Vijay Krishna, Kapil Vyas, Rajkumar Palwai, 2009, 2009 22nd International Conference on VLSI Design.

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, 2010, 2010 23rd International Conference on VLSI Design.

A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

Manish Jain, Kapil Vyas, Mahabaleshwara, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).