OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization

Accurate characterization of real device samples is essential for understanding the true potential of the emerging non-volatile memories (NVMs) and identifying their optimal placement in the memory hierarchy. Even though, NVM devices are now available from different manufacturers, lack of an appropriate NVM controller and evaluation platform in the public domain is the main challenge in extracting empirical data from these real devices. In this paper, we present Open-NVM, an open-sourced, highly configurable FPGA based evaluation/characterization platform for various NVM technologies. Through our OpenNVM, this work reveals important low-level NVM characteristics, including i) static and dynamic latency disparity, ii) error rate variation, iii) power consumption behavior, vi) interrelationship between frequency and NVM operational current. In addition, we also examine state-of-the-art write-once-memory (WOM) codes on a real NVM device and study diverse system-level performance impacts based on our findings. All FPGA source code and detailed information of our hardware design is ready to be open-sourced and downloaded for free.

[1]  Jason Cong,et al.  Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Sunghoon Kim,et al.  7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[3]  Jason Heidecker MRAM Technology Status , 2013 .

[4]  Eun-Seok Choi,et al.  A Novel 3D Cell Array Architecture for Terra-Bit NAND Flash Memory , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[5]  Christopher Frost,et al.  Better I/O through byte-addressable, persistent memory , 2009, SOSP '09.

[6]  Yitzhak Birk,et al.  Retired-page utilization in write-once memory — A coding perspective , 2013, 2013 IEEE International Symposium on Information Theory.

[7]  Adi Shamir,et al.  How to Reuse a "Write-Once" Memory , 1982, Inf. Control..

[8]  Paul H. Siegel,et al.  Error characterization and coding schemes for flash memories , 2010, 2010 IEEE Globecom Workshops.

[9]  Yiran Chen,et al.  Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[11]  Chris Fallin,et al.  Memory power management via dynamic voltage/frequency scaling , 2011, ICAC '11.

[12]  Anthony J. Kenyon,et al.  Resistive switching in silicon sub-oxide films , 2012 .

[13]  Lara Dolecek,et al.  Non-binary WOM-codes for multilevel flash memories , 2011, 2011 IEEE Information Theory Workshop.

[14]  Eitan Yaakobi,et al.  Write Once, Get 50% Free: Saving SSD Erase Costs Using WOM Codes , 2015, FAST.

[15]  Massoud Pedram,et al.  Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times , 2005 .

[16]  Gérard D. Cohen,et al.  Linear binary code for write-once memories , 1986, IEEE Trans. Inf. Theory.

[17]  Mircea R. Stan,et al.  Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[18]  Adam Leventhal,et al.  Flash storage memory , 2008, CACM.

[19]  Paul H. Siegel,et al.  Characterizing flash memory: Anomalies, observations, and applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[20]  Gyuyeol Kong,et al.  Cell-to-Cell Interference Compensation Schemes Using Reduced Symbol Pattern of Interfering Cells for MLC NAND Flash Memory , 2013, IEEE Transactions on Magnetics.

[21]  Mahmut T. Kandemir,et al.  Evaluating STT-RAM as an energy-efficient main memory alternative , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).