Timing-driven logic bi-decomposition

An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expressions with smaller depths than the ones obtained by state-of-the-art techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.

[1]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[2]  Shih-Chieh Chang,et al.  Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Rajeev Murgai,et al.  Delay estimation and optimization of logic circuits: a survey , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[4]  Saburo Muroga,et al.  Timing optimization for multi-level combinational networks , 1990, DAC '90.

[5]  Christoph Scholl,et al.  Functional Decomposition With Application to FPGA Syn-thesis , 2001 .

[6]  Robert K. Brayton,et al.  Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[7]  Tsutomu Sasao,et al.  FPGA Design by Generalized Functional Decomposition , 1993 .

[8]  Jean-Loup Baer,et al.  Compilation of arithmetic expressions for parallel computations , 1968, IFIP Congress.

[9]  Yosinori Watanabe,et al.  Logic decomposition during technology mapping , 1995, ICCAD.

[10]  James C. Beatty.  An axiomatic approach to code optimization for expressions , 1972, JACM.

[11]  Wojciech Rytter,et al.  Efficient parallel algorithms , 1988 .

[12]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, DAC.

[13]  Robert K. Brayton,et al.  Delay optimization of combinational logic circuits by clustering and partial collapsing , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[14]  Ankur Srivastava,et al.  Timing driven gate duplication: complexity issues and algorithms , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[15]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  David L. Kuck,et al.  The Structure of Computers and Computations , 1978 .

[17]  Hiroshi Sawada,et al.  New methods to find optimal non-disjoint bi-decompositions , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[18]  Bernd Steinbach,et al.  An algorithm for bi-decomposition of logic functions , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[19]  Carl Sechen,et al.  Quasi-algebraic decompositions of switching functions , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[20]  Robert K. Brayton,et al.  Delay-optimal technology mapping by DAG covering , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[21]  Henrik Reif Andersen,et al.  Boolean Expression Diagrams , 2002, Inf. Comput..

[22]  Massoud Pedram,et al.  OBDD-based function decomposition: algorithms and implementation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Sze-Tsen Hu.  ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .

[24]  Janusz Rajski,et al.  A method for concurrent decomposition and factorization of Boolean expressions , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[25]  Kenneth L. McMillan,et al.  Approximation and decomposition of binary decision diagrams , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[26]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .