Improving multilevel PCM reliability through age-aware reading and writing strategies
暂无分享,去创建一个
[1] Wei Xu,et al. A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Hsien-Hsin S. Lee,et al. Tri-level-cell phase change memory: toward an efficient and reliable memory system , 2013, ISCA.
[3] Rudolf Ahlswede,et al. Unidirectional error control codes and related combinatorial problems , 2002 .
[4] Anxiao Jiang,et al. Bit-fixing codes for multi-level cells , 2012, 2012 IEEE Information Theory Workshop.
[5] E. Eleftheriou,et al. Drift-Tolerant Multilevel Phase-Change Memory , 2011, 2011 3rd IEEE International Memory Workshop (IMW).
[6] Jiwu Shu,et al. Aegis: Partitioning data block for efficient recovery of stuck-at-faults in phase change memory , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[7] D. Ielmini,et al. Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories , 2007, IEEE Transactions on Electron Devices.
[8] Rami G. Melhem,et al. RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory , 2012, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012).
[9] Chaitali Chakrabarti,et al. Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM , 2012, 2012 IEEE Workshop on Signal Processing Systems.
[10] 裕幸 飯田,et al. International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .
[11] D. Ielmini,et al. Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part I: Experimental Study , 2009, IEEE Transactions on Electron Devices.
[12] Hsien-Hsin S. Lee,et al. SAFER: Stuck-At-Fault Error Recovery for Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[13] Jehoshua Bruck,et al. Codes for Asymmetric Limited-Magnitude Errors With Application to Multilevel Flash Memories , 2010, IEEE Transactions on Information Theory.
[14] Tao Li,et al. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system , 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN).