Accurate and efficient predicate analysis with binary decision diagrams

Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and to enhance optimization, provided that compilers can utilize it effectively. Previous work has established the need for accurate, direct predicate analysis and has demonstrated a few useful techniques, but has not provided an efficient, general framework. The paper presents the Predicate Analysis System (PAS), which maps knowledge of predicate and condition relations in general control flow onto a convenient logical substrate, the reduced ordered binary decision diagram. PAS is the first such framework to demonstrate direct, accurate, and efficient analysis of arbitrary condition and predicate define networks in arbitrary control flow.

[1]  Saburo Muroga,et al.  Binary Decision Diagrams , 2000, The VLSI Handbook.

[2]  Richard Johnson,et al.  Analysis techniques for predicated code , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[3]  Scott A. Mahlke,et al.  The program decision logic approach to predicated execution , 1999, ISCA.

[4]  John W. Sias,et al.  Condition Awareness Support For Predicate Analysis And Optimization , 1999 .

[5]  David A. Padua,et al.  Gated SSA-based demand-driven symbolic analysis for parallelizing compilers , 1995, ICS '95.

[6]  Alexandre E. Eichenberger,et al.  Register allocation for predicated code , 1995, Proceedings of the 28th Annual International Symposium on Microarchitecture.

[7]  Dirk Grunwald,et al.  A system level perspective on branch architecture performance , 1995, Proceedings of the 28th Annual International Symposium on Microarchitecture.

[8]  Larry Carter,et al.  Predicated static single assignment , 1999, 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425).

[9]  Scott A. Mahlke,et al.  A framework for balancing control flow and predication , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[10]  E BryantRandal.  Graph-Based Algorithms for Boolean Function Manipulation , 1986 .

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  Kenneth J. Supowit,et al.  Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1987, 24th ACM/IEEE Design Automation Conference.

[13]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[14]  Scott A. Mahlke,et al.  Control CPR: a branch height reduction optimization for EPIC architectures , 1999, PLDI '99.

[15]  C. Leonard Berman,et al.  Circuit width, register allocation, and ordered binary decision diagrams , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  M. Schlansker,et al.  On Predicated Execution , 1991 .

[17]  Scott A. Mahlke,et al.  Integrated predicated and speculative execution in the IMPACT EPIC architecture , 1998, ISCA.

[18]  Roy Dz-Ching Ju,et al.  Global predicate analysis and its application to register allocation , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[19]  Scott A. Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 25.

[20]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[21]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[22]  R. Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.

[23]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.