Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of folding, unrolling, and pipelining. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance, and the characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.

[1]  Kris Gaj,et al.  ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[2]  Kris Gaj,et al.  Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs , 2010, CHES.

[3]  Nancy Grand-Est.  A Low-Area yet Performant FPGA Implementation of Shabal , 2010 .

[4]  P. Schaumont,et al.  How Can We Conduct " Fair and Consistent " Hardware Evaluation for SHA-3 Candidate ? , 2010 .

[5]  William P. Marnane,et al.  FPGA Implementations of the Round Two SHA-3 Candidates , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[6]  Paris Kitsos,et al.  BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[7]  Aggelos Kiayias,et al.  Polynomial Reconstruction Based Cryptography , 2001, Selected Areas in Cryptography.

[8]  Martin Feldhofer,et al.  High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Gröstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein , 2009, IACR Cryptol. ePrint Arch..

[9]  Abdulkadir Akin,et al.  Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing , 2010, SIN.

[10]  Luca Henzen,et al.  Developing a Hardware Evaluation Method for SHA-3 Candidates , 2010, CHES.

[11]  Elaine B. Barker,et al.  Report on the Development of the Advanced Encryption Standard (AES) , 2001, Journal of research of the National Institute of Standards and Technology.

[12]  Eiji Okamoto,et al.  A Compact FPGA Implementation of the SHA-3 Candidate ECHO , 2010, IACR Cryptol. ePrint Arch..

[13]  Xu Guo,et al.  Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations , 2010 .

[14]  Stefan Mangard,et al.  Cryptographic Hardware and Embedded Systems, CHES 2010, 12th International Workshop, Santa Barbara, CA, USA, August 17-20, 2010. Proceedings , 2010, CHES.