On the adders with minimum tests
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[1] Bernd Becker. Efficient Testing of Optimal Time Adders , 1988, IEEE Trans. Computers.
[2] David A. Huffman,et al. Testing for Faults in Cellular Logic Arrays , 1972 .
[3] Saburo Muroga,et al. Logic design and switching theory , 1979 .
[4] Irith Pomeranz,et al. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] John P. Hayes,et al. Test-set preserving logic transformations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[6] Janak H. Patel,et al. A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders , 1987, IEEE Transactions on Computers.
[7] Janusz Rajski,et al. A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Saburo Muroga,et al. Optimal One-Bit Full Adders With Different Types of Gates , 1974, IEEE Transactions on Computers.
[9] Richard F. Tinder. Digital Engineering Design: A Modern Approach , 1991 .
[10] Frederick J. Hill,et al. Introduction to Switching Theory and Logical Design , 1968 .
[11] Se June Hong,et al. Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks , 1971, IEEE Transactions on Computers.
[12] A. Gill. SWITCHING AND AUTOMATA THEORY. , 1970 .
[13] William H. Kautz. Testing for Faults in Combinational Cellular Logic Arrays , 1967, SWAT.
[14] Rolf Drechsler,et al. A fast optimal robust path delay fault testable adder , 1996, Proceedings ED&TC European Design and Test Conference.
[15] Rolf Drechsler,et al. On the generation of area-time optimal testable adders , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..