A High Reliability Sense Amplifier for Computing In-Memory with STT-MRAM

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the re...

[1]  Jacques-Olivier Klein,et al.  Design considerations and strategies for high-reliable STT-MRAM , 2011, Microelectron. Reliab..

[2]  Jacques-Olivier Klein,et al.  Design of embedded MRAM macros for memory-in-logic applications , 2010, GLSVLSI '10.

[3]  S. Ikeda,et al.  2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read , 2008, IEEE Journal of Solid-State Circuits.

[4]  Meng-Fan Chang,et al.  A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM , 2018, IEEE Access.

[5]  Yuan Xie,et al.  Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Chaitali Chakrabarti,et al.  Random variability modeling and its impact on scaled CMOS circuits , 2010 .

[7]  Santosh Kumar Vishvakarma,et al.  On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells , 2018, IEEE Transactions on Semiconductor Manufacturing.

[8]  Houman Homayoun,et al.  Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging , 2016, Microelectron. Reliab..

[9]  Masanori Hashimoto,et al.  Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[10]  Anand Raghunathan,et al.  Computing in Memory With Spin-Transfer Torque Magnetic RAM , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[12]  Jacques-Olivier Klein,et al.  Failure and reliability analysis of STT-MRAM , 2012, Microelectron. Reliab..

[13]  A. Fert,et al.  Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance , 2017, Nature Communications.

[14]  Yu Cao,et al.  Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[15]  A. Fert,et al.  The emergence of spin electronics in data storage. , 2007, Nature materials.

[16]  Mehdi Baradaran Tahoori,et al.  Fault tolerant approximate computing using emerging non-volatile spintronic memories , 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

[17]  Youguang Zhang,et al.  Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology , 2015, IEEE Transactions on Electron Devices.

[18]  Shaahin Angizi,et al.  IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch , 2018, IEEE Transactions on Magnetics.

[19]  H. Ohno,et al.  Tunnel magnetoresistance of 604% at 300K by suppression of Ta diffusion in CoFeB∕MgO∕CoFeB pseudo-spin-valves annealed at high temperature , 2008 .

[20]  Shaahin Angizi,et al.  Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction , 2017, 2017 IEEE International Conference on Computer Design (ICCD).

[21]  Taejoong Song,et al.  28-nm 1T-1MTJ 8Mb 64 I/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[22]  Aida Todri,et al.  A high-reliability and low-power computing-in-memory implementation within STT-MRAM , 2018, Microelectron. J..

[23]  Li Zhang,et al.  Design and analysis of the reference cells for STT-MRAM , 2013, IEICE Electron. Express.

[24]  S. Rauch,et al.  Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.

[25]  Aida Todri,et al.  A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM , 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[26]  Yiran Chen,et al.  Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes , 2015, IEEE Transactions on Electron Devices.

[27]  Weisheng Zhao,et al.  High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits , 2009, IEEE Transactions on Magnetics.

[28]  Zhaohao Wang,et al.  High-Density NAND-Like Spin Transfer Torque Memory With Spin Orbit Torque Erase Operation , 2018, IEEE Electron Device Letters.

[29]  Yiran Chen,et al.  A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme , 2012, IEEE Journal of Solid-State Circuits.