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Srdjan Capkun | Ahmad-Reza Sadeghi | Tommaso Frassetto | Kari Kostiainen | Alexandra Dmitrienko | Urs Müller | Ferdinand Brasser | Srdjan Capkun | Kari Kostiainen | A. Sadeghi | A. Dmitrienko | Ferdinand Brasser | Urs Müller | Tommaso Frassetto | Ahmad Sadeghi
[1] Kevin W. Hamlen,et al. Binary stirring: self-randomizing instruction addresses of legacy x86 binary code , 2012, CCS.
[2] Galen C. Hunt,et al. Shielding Applications from an Untrusted Cloud with Haven , 2014, OSDI.
[3] Jack W. Davidson,et al. ILR: Where'd My Gadgets Go? , 2012, 2012 IEEE Symposium on Security and Privacy.
[4] M. Bellare,et al. The FFX Mode of Operation for Format-Preserving Encryption Draft 1 . 1 , 2010 .
[5] G. Edward Suh,et al. AEGIS: architecture for tamper-evident and tamper-resistant processing , 2003, ICS.
[6] Elaine Shi,et al. PHANTOM: practical oblivious computation in a secure processor , 2013, CCS.
[7] Elaine Shi,et al. Constants Count: Practical Improvements to Oblivious RAM , 2015, USENIX Security Symposium.
[8] Ahmad-Reza Sadeghi,et al. Secure Multiparty Computation from SGX , 2017, Financial Cryptography.
[9] Julian Stecklina,et al. LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels , 2018, ArXiv.
[10] Per Larsen,et al. Thwarting Cache Side-Channel Attacks Through Dynamic Software Diversity , 2015, NDSS.
[11] Ahmad-Reza Sadeghi,et al. Trusted Virtual Domains - Design, Implementation and Lessons Learned , 2009, INTRUST.
[12] Adrian Perrig,et al. TrustVisor: Efficient TCB Reduction and Attestation , 2010, 2010 IEEE Symposium on Security and Privacy.
[13] Ruby B. Lee,et al. Random Fill Cache Architecture , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[14] Daniel Gruss,et al. Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory , 2017, USENIX Security Symposium.
[15] Marek Chrobak,et al. A low-cost memory remapping scheme for address bus protection , 2006, 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[16] Elaine Shi,et al. GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation , 2015, ASPLOS.
[17] Herbert Bos,et al. Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks , 2018, USENIX Security Symposium.
[18] Thomas Eisenbarth,et al. MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations in SGX , 2018, CT-RSA.
[19] Ariel J. Feldman,et al. Lest we remember: cold-boot attacks on encryption keys , 2008, CACM.
[20] Peter Gutmann,et al. Data Remanence in Semiconductor Devices , 2001, USENIX Security Symposium.
[21] Marcus Peinado,et al. T-SGX: Eradicating Controlled-Channel Attacks Against Enclave Programs , 2017, NDSS.
[22] Marcus Peinado,et al. Controlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems , 2015, 2015 IEEE Symposium on Security and Privacy.
[23] Elaine Shi,et al. Memory Trace Oblivious Program Execution , 2013, 2013 IEEE 26th Computer Security Foundations Symposium.
[24] Avesta Sasan,et al. Advances and throwbacks in hardware-assisted security: special session , 2018, CASES.
[25] Ashay Rane,et al. Raccoon: Closing Digital Side-Channels through Obfuscated Execution , 2015, USENIX Security Symposium.
[26] Christos Gkantsidis,et al. VC3: Trustworthy Data Analytics in the Cloud Using SGX , 2015, 2015 IEEE Symposium on Security and Privacy.
[27] Christos Gkantsidis,et al. Observing and Preventing Leakage in MapReduce , 2015, CCS.
[28] Rüdiger Kapitza,et al. Telling Your Secrets without Page Faults: Stealthy Page Table-Based Attacks on Enclaved Execution , 2017, USENIX Security Symposium.
[29] Ahmad-Reza Sadeghi,et al. Just-In-Time Code Reuse: On the Effectiveness of Fine-Grained Address Space Layout Randomization , 2013, 2013 IEEE Symposium on Security and Privacy.
[30] Mengyuan Li,et al. STACCO: Differentially Analyzing Side-Channel Traces for Detecting SSL/TLS Vulnerabilities in Secure Enclaves , 2017, CCS.
[31] Johannes Götzfried,et al. Cache Attacks on Intel SGX , 2017, EUROSEC.
[32] Yuan Xiao,et al. SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution , 2018, 2019 IEEE European Symposium on Security and Privacy (EuroS&P).
[33] Srinivas Devadas,et al. Sanctum: Minimal Hardware Extensions for Strong Software Isolation , 2016, USENIX Security Symposium.
[34] Jeff Seibert,et al. Information Leaks Without Memory Disclosures: Remote Side Channel Attacks on Diversified Code , 2014, CCS.
[35] Dan Boneh,et al. Hacking Blind , 2014, 2014 IEEE Symposium on Security and Privacy.
[36] Ling Ren,et al. Path ORAM , 2012, J. ACM.
[37] Herbert Bos,et al. Malicious Management Unit: Why Stopping Cache Attacks in Software is Harder Than You Think , 2018, USENIX Security Symposium.
[38] Stefan Mangard,et al. Malware Guard Extension: Using SGX to Conceal Cache Attacks , 2017, DIMVA.
[39] Rafail Ostrovsky,et al. Software protection and simulation on oblivious RAMs , 1996, JACM.
[40] Srinivas Devadas,et al. Intel SGX Explained , 2016, IACR Cryptol. ePrint Arch..
[41] Mauro Conti,et al. The Guard's Dilemma: Efficient Code-Reuse Attacks Against Intel SGX , 2018, USENIX Security Symposium.
[42] William W. Streilein,et al. Timely Rerandomization for Mitigating Memory Disclosures , 2015, CCS.
[43] Ruby B. Lee,et al. New models of cache architectures characterizing information leakage from cache side channels , 2014, ACSAC.
[44] Srdjan Capkun,et al. Software Grand Exposure: SGX Cache Attacks Are Practical , 2017, WOOT.
[45] Carlos V. Rozas,et al. Innovative instructions and software model for isolated execution , 2013, HASP '13.
[46] Michael Hamburg,et al. Spectre Attacks: Exploiting Speculative Execution , 2018, 2019 IEEE Symposium on Security and Privacy (SP).
[47] Ruby B. Lee,et al. New cache designs for thwarting software cache-based side channel attacks , 2007, ISCA '07.
[48] Yan Solihin,et al. ObfusMem: A low-overhead access obfuscation for trusted memories , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).
[49] Donald E. Porter,et al. Graphene-SGX: A Practical Library OS for Unmodified Applications on SGX , 2017, USENIX Annual Technical Conference.
[50] Yuval Yarom,et al. CacheBleed: a timing attack on OpenSSL constant-time RSA , 2016, Journal of Cryptographic Engineering.
[51] Dan Boneh,et al. Architectural support for copy and tamper resistant software , 2000, SIGP.
[52] Ruby B. Lee,et al. A novel cache architecture with enhanced performance and security , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[53] Marcus Peinado,et al. Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing , 2016, USENIX Security Symposium.
[54] Ahmad-Reza Sadeghi,et al. VoiceGuard: Secure and Private Speech Processing , 2018, INTERSPEECH.
[55] Dan Page,et al. Partitioned Cache Architecture as a Side-Channel Defence Mechanism , 2005, IACR Cryptology ePrint Archive.
[56] Oded Goldreich,et al. Towards a theory of software protection and simulation by oblivious RAMs , 1987, STOC.
[57] Jonathan M. McCune,et al. Efficient TCB Reduction and Attestation , 2009 .
[58] Sanjit A. Seshia,et al. A compiler and verifier for page access oblivious computation , 2017, ESEC/SIGSOFT FSE.
[59] Nael B. Abu-Ghazaleh,et al. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks , 2012, TACO.
[60] Thomas F. Wenisch,et al. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution , 2018, USENIX Security Symposium.
[61] Ahmad-Reza Sadeghi,et al. HardIDX: Practical and Secure Index with SGX , 2017, DBSec.
[62] Ruby B. Lee,et al. Covert and Side Channels Due to Processor Architecture , 2006, 2006 22nd Annual Computer Security Applications Conference (ACSAC'06).
[63] Stefanos Kaxiras,et al. Non deterministic caches: a simple and effective defense against side channel attacks , 2008, Des. Autom. Embed. Syst..
[64] Michael Hamburg,et al. Meltdown: Reading Kernel Memory from User Space , 2018, USENIX Security Symposium.
[65] Jean-Pierre Seifert,et al. Deconstructing new cache designs for thwarting software cache-based side channel attacks , 2008, CSAW '08.
[66] Michael T. Goodrich,et al. Privacy-preserving group data access via stateless oblivious RAM simulation , 2011, SODA.
[67] Junfeng Yang,et al. Shuffler: Fast and Deployable Continuous Code Re-Randomization , 2016, OSDI.
[68] Peng Ning,et al. Address Space Layout Permutation (ASLP): Towards Fine-Grained Randomization of Commodity Software , 2006, 2006 22nd Annual Computer Security Applications Conference (ACSAC'06).
[69] Michael K. Reiter,et al. Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu , 2017, AsiaCCS.
[70] Jan Reineke,et al. CacheAudit: A Tool for the Static Analysis of Cache Side Channels , 2013, TSEC.
[71] Ittai Anati,et al. Innovative Technology for CPU Based Attestation and Sealing , 2013 .
[72] Angelos D. Keromytis,et al. Smashing the Gadgets: Hindering Return-Oriented Programming Using In-place Code Randomization , 2012, 2012 IEEE Symposium on Security and Privacy.
[73] Tao Zhang,et al. HIDE: an infrastructure for efficiently protecting information leakage on the address bus , 2004, ASPLOS XI.
[74] Dan Page,et al. Defending against cache-based side-channel attacks , 2003, Inf. Secur. Tech. Rep..
[75] Ruby B. Lee,et al. CloudRadar: A Real-Time Side-Channel Attack Detection System in Clouds , 2016, RAID.
[76] Patrick Simmons,et al. Security through amnesia: a software-based solution to the cold boot attack on disk encryption , 2011, ACSAC '11.
[77] Tilo Müller,et al. PRIME: private RSA infrastructure for memory-less encryption , 2013, ACSAC.
[78] Tao Zhang,et al. Hardware assisted control flow obfuscation for embedded processors , 2004, CASES '04.
[79] Jean-Pierre Seifert,et al. Hardware-software integrated approaches to defend against software cache-based side channel attacks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.
[80] Bhavani M. Thuraisingham,et al. Securing Data Analytics on SGX with Randomization , 2017, ESORICS.
[81] Adi Shamir,et al. Cache Attacks and Countermeasures: The Case of AES , 2006, CT-RSA.
[82] Avesta Sasan,et al. Special Session: Advances and Throwbacks in Hardware-Assisted Security , 2018, 2018 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).
[83] Gorka Irazoqui Apecechea,et al. CacheZoom: How SGX Amplifies The Power of Cache Attacks , 2017, CHES.
[84] Ahmad-Reza Sadeghi,et al. JITGuard: Hardening Just-in-time Compilers with SGX , 2017, CCS.
[85] Insik Shin,et al. SGX-Shield: Enabling Address Space Layout Randomization for SGX Programs , 2017, NDSS.
[86] Marco Chiappetta,et al. Real time detection of cache-based side-channel attacks using hardware performance counters , 2016, Appl. Soft Comput..
[87] Andrew C. Simpson,et al. Exploring the use of Intel SGX for Secure Many-Party Applications , 2016, SysTEX@Middleware.
[88] Hovav Shacham,et al. Return-Oriented Programming: Systems, Languages, and Applications , 2012, TSEC.
[89] Andreas Dewald,et al. TRESOR Runs Encryption Securely Outside RAM , 2011, USENIX Security Symposium.
[90] Frank Piessens,et al. Breaking the memory secrecy assumption , 2009, EUROSEC '09.
[91] Ahmad-Reza Sadeghi,et al. Gadge me if you can: secure and efficient ad-hoc instruction-level randomization for x86 and ARM , 2013, ASIA CCS '13.
[92] Christopher W. Fletcher,et al. ZeroTrace : Oblivious Memory Primitives from Intel SGX , 2018, NDSS.
[93] Sebastian Nowozin,et al. Oblivious Multi-Party Machine Learning on Trusted Processors , 2016, USENIX Security Symposium.