On the Minimization of Longest Path Length for Decision Diagrams

In this paper, we consider the minimization of the longest path length (LPL) for binary decision diagrams (BDDs) and heterogeneous multi-valued decision diagrams (MDDs). Experimental results show that: (1) For many logic functions, node minimization of BDDs also minimizes the LPLs of BDDs. (2) When we use heterogeneous MDDs for representing logic functions and minimize the memory sizes of heterogeneous MDDs, we can reduce both memory sizes and LPLs to 86% and 72% of corresponding BDDs, respectively. On the other hand, when the memory limitations are set to the memory sizes of BDDs, the LPLs can be reduced to 54% of BDDs.

[1]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[2]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.

[3]  TingTing Hwang,et al.  Binary decision diagram with minimum expected path length , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Robert K. Brayton,et al.  Software synthesis from synchronous specifications using logic simulation techniques , 2002, DAC '02.

[5]  Nagisa Ishiura,et al.  Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.

[6]  Adnan Aziz,et al.  Performance driven synthesis for pass-transistor logic , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[7]  Shinobu Nagayama,et al.  On the minimization of average path lengths for heterogeneous MDDs [multi-valued decision diagrams] , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[8]  Tiziano Villa,et al.  Multi-valued decision diagrams: theory and applications , 1998 .

[9]  Rolf Drechsler,et al.  Minimization of the expected path length in BDDs based on local changes , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[10]  S. Nagayama.  Code generation for embedded systems using heterogeneous MDDs , 2003 .

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Logic synthesis for large pass transistor circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[12]  Albert Mo Kim Cheng,et al.  Real-time scheduling of hierarchical reward-based tasks , 2003, The 9th IEEE Real-Time and Embedded Technology and Applications Symposium, 2003. Proceedings..

[13]  Hans A. Hansson,et al.  Using measurements to derive the worst-case execution time , 2000, Proceedings Seventh International Conference on Real-Time Computing Systems and Applications.

[14]  Shin-ichi Minato,et al.  Minimum-Width Method of Variable Ordering for Binary Decision Diagrams , 1992 .

[15]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[16]  Saburo Muroga,et al.  Logic design and switching theory , 1979 .

[17]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[18]  Alexander Saldanha,et al.  Fast discrete function evaluation using decision diagrams , 1995, ICCAD.

[19]  Shinobu Nagayama,et al.  Compact representations of logic functions using heterogeneous MDDs , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

[20]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[21]  Sharad Malik,et al.  Fast functional simulation using branching programs , 1995, ICCAD.

[22]  Bernd Becker,et al.  On the generation of multiplexer circuits for pass transistor logic , 2000, DATE '00.

[23]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[24]  Shinobu Nagayama,et al.  Minimization of average path length in BDDs by variable reordering , 2003 .

[25]  Shinobu Nagayama,et al.  Minimization of memory size for heterogeneous MDDs , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[26]  Luciano Lavagno,et al.  Synthesis of Software Programs for Embedded Control Applications , 1999, 32nd Design Automation Conference.

[27]  Thomas Nolte,et al.  Probabilistic worst-case response-time analysis for the controller area network , 2003, The 9th IEEE Real-Time and Embedded Technology and Applications Symposium, 2003. Proceedings..