A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks

Over the last decades computer-aided engineering tools have been developed and improved in order to raise productivity in the chip design business. At the same time reconfigurable microelectronic devices known as field programmable gates arrays (FPGAs) evolved into powerful platforms for the implementation of complex embedded systems. Up to now, these design tools do not support a consistent design strategy for the development of side-channel resistant hardware implementations of cryptographic algorithms. In order to close this gap, we present a novel architecture denoted as Mutating Runtime Architecture and a dedicated design flow aimed to support system designers in implementing cryptographic devices hardened against side-channel attacks (SCA). Our contributions are generic in the sense that they allow to uniformly harden symmetric as well as asymmetric cryptographic algorithms against power analysis attacks. In addition to an introduction of fundamental concepts, construction methods for multiple countermeasures, and the resulting flexible cipher architecture, we present a case study.

[1]  Takeshi Sugawara,et al.  Differential power analysis of AES ASIC implementations with various S-box circuits , 2009, 2009 European Conference on Circuit Theory and Design.

[2]  Sorin A. Huss,et al.  Side-channel resistant AES architecture utilizing randomized composite field representations , 2012, 2012 International Conference on Field-Programmable Technology.

[3]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.

[4]  F. Madlener,et al.  Novel hardening techniques against differential power analysis for multiplication in GF(2n) , 2009, 2009 International Conference on Field-Programmable Technology.

[5]  Stefan Mangard,et al.  Side-Channel Leakage of Masked CMOS Gates , 2005, CT-RSA.

[6]  Sorin A. Huss,et al.  Virtualization within a Parallel Array of Homogeneous Processing Units , 2010, ARC.

[7]  Werner Schindler,et al.  A stochastic method for security evaluation of cryptographic FPGA implementations , 2010, 2010 International Conference on Field-Programmable Technology.

[8]  Wieland Fischer,et al.  Masking at Gate Level in the Presence of Glitches , 2005, CHES.

[9]  Yi Wang,et al.  FPGA Implementations of the AES Masked Against Power Analysis Attacks , 2011 .

[10]  Stefan Mangard,et al.  Successfully Attacking Masked AES Hardware Implementations , 2005, CHES.

[11]  Akashi Satoh,et al.  An Optimized S-Box Circuit Architecture for Low Power AES Design , 2002, CHES.

[12]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[13]  Ingrid Verbauwhede,et al.  Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration , 2008, CHES.

[14]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[15]  David R. Canright,et al.  A very compact Rijndael S-box , 2005 .

[16]  Luca Benini,et al.  Energy-aware design techniques for differential power analysis protection , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[17]  Sorin A. Huss,et al.  A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n) , 2002, CHES.

[18]  Daniel D. Gajski,et al.  Embedded System Design: Modeling, Synthesis and Verification , 2013 .

[19]  Christof Paar,et al.  Understanding Cryptography: A Textbook for Students and Practitioners , 2009 .

[20]  Luca Benini,et al.  A novel architecture for power maskable arithmetic units , 2003, GLSVLSI '03.