3D die-stacked DRAM thermal management via task allocation and core pipeline control

[1]  Jie Meng,et al.  Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints , 2012, DAC Design Automation Conference 2012.

[2]  Tao Zhang,et al.  NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems , 2015, IEEE Computer Architecture Letters.

[3]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[4]  Kevin Skadron,et al.  HotSpot 6.0: Validation, Acceleration and Extension , 2015 .

[5]  Houman Homayoun,et al.  Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[6]  Houman Homayoun,et al.  Temperature aware thread migration in 3D architecture with stacked DRAM , 2013, International Symposium on Quality Electronic Design (ISQED).

[7]  Vijay Janapa Reddi,et al.  Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[8]  Dawei Li,et al.  Adaptive thermal management for 3D ICs with stacked DRAM caches , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  Young-Hyun Jun,et al.  A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.

[10]  TingTing Hwang,et al.  Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC) , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Zhao Zhang,et al.  Thermal modeling and management of DRAM memory systems , 2007, ISCA '07.

[12]  A. Kumar,et al.  A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[13]  Dong Li,et al.  Integrated Thermal Analysis for Processing In Die-Stacking Memory , 2016, MEMSYS.

[14]  Kevin Skadron,et al.  Recent thermal management techniques for microprocessors , 2012, CSUR.

[15]  Bruce Jacob,et al.  DRAM Refresh Mechanisms, Penalties, and Trade-Offs , 2016, IEEE Transactions on Computers.

[16]  Song Liu,et al.  Hardware/software techniques for DRAM thermal management , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.