Field programmable gate array/system on a programmable chip-based implementation of model predictive controller

To improve the on-line computational performance of model predictive control (MPC) for fast systems and/or embedded systems, this study proposes a novel scheme for the MPC controller implementation based on field programmable gate array (FPGA) and system on a programmable chip (SOPC) technology. A Nios II processor clocked at 150 MHz is embedded into the FPGA chip. A C/C++ model of the MPC algorithm which is run in the Nios II processor is created. The dual method is adopted to solve the quadratic programming (QP) problem. Based on FPGA and dSPACE®, a rapid prototyping platform is introduced to test and verify the function and computational performance of the MPC controller. Real-time simulation results of controlling a throttle model show that a reasonable size of constrained MPC controller can be implemented on the used RCIII FPGA board.